Patent US3765013A successfully refreshed from Google Patents.
US3765013A
Expired / Lapsed
US
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Self synchronous serial encoder/decoder
Assignee: United States Department of the Navy
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Filing: 1972-06-23
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Granted: 1973-10-09
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Expires: 1992-06-23
Abstract
Abstract A device to provide a simple means of translating a parallel nbit data word from a counter or the like to a serial format which is suitable for single channel recording or transmission over a single wire. Also, this device permits the decoding of serial data back to parallel form independent of the exact time location of the leading bit of the serial code.
Inventors
- 👤 L Leibowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:21
CPC Classifications
H; H03; H03M; H03M9/00; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/45
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
136 words
A system for translating a parallel n-bit data word into a serial format capable of single line transmission without a time reference marker bit comprising: parallel/serial shift register means for accepting an n-bit word in parallel format and converting it into serial format as long as said means are enabled; modulo counter means for enabling said shift register means for a time approximately equal to the time required to sequentially clock the n-bit parallel word into serial form from the most significant bit to the least significant bit; pulse generating means for sequentially generating a pulse of length T1 where a ''''0'''' is present in the most significant bit position in said serial format and a pulse of length T2 where a ''''1'''' is present in the most significant bit position to form a serial word.
Claim 2
Independent Claim
136 words
A system for translating a parallel n-bit data word into a serial format capable of single line transmission without a time reference marker bit comprising: parallel/serial shift register means for accepting an n-bit word in parallel format and converting it into serial format as long as said means are enabled; modulo counter means for enabling said shift register means for a time approximately equal to the time required to sequentially clock the n-bit parallel word into serial form from the most significant bit to the least significant bit; pulse generating means for sequentially generating a pulse of length T1 where a ''''0'''' is present in the most significant bit position in said serial format and a pulse of length T2 where a ''''1'''' is present in the most significant bit position to form a serial word.
Claim 3
Independent Claim
243 words
A system for translating a parallel n-bit word into a serial format capable of single line transmission without a time reference marker bit and retranslating said serial format back into an n-bit parallel word, comprising: parallel/serial shift register means for accepting the n-bit word in parallel format and converting it into serial format as long as said means are enabled; modulo counter means for enabling said shift register means for a time approximately equal to the time required to sequentially clock the n-bit parallel word into serial form from the most significant bit to the least significant bit; pulse generating means for sequentially generating a pulse of length T1 where a ''''0'''' is present in the most significant bit position in said serial format and a pulse of length T2 where a ''''1'''' is present in the most significant bit position to form a serial word; transmission line means connected to said pulse generating means to permit transmission of said word; a second parallel/serial shift register means coupled to said transmission line means for accepting the serial word; comparing means coupled to said shift register means and said transmission line means for determining if the most significant bit is either of length T1 or T2; shifting means coupled to said comparing means for sequentially loading said parallel/serial shift register means with an ''''0'''' when a pulse of width T1 is present and with a ''''1'''' when a pulse of width T2 is present.
Claim 4
Independent Claim
243 words
A system for translating a parallel n-bit word into a serial format capable of single line transmission without a time reference marker bit and retranslating said serial format back into an n-bit parallel word, comprising: parallel/serial shift register means for accepting the n-bit word in parallel format and converting it into serial format as long as said means are enabled; modulo counter means for enabling said shift register means for a time approximately equal to the time required to sequentially clock the n-bit parallel word into serial form from the most significant bit to the least significant bit; pulse generating means for sequentially generating a pulse of length T1 where a ''''0'''' is present in the most significant bit position in said serial format and a pulse of length T2 where a ''''1'''' is present in the most significant bit position to form a serial word; transmission line means connected to said pulse generating means to permit transmission of said word; a second parallel/serial shift register means coupled to said transmission line means for accepting the serial word; comparing means coupled to said shift register means and said transmission line means for determining if the most significant bit is either of length T1 or T2; shifting means coupled to said comparing means for sequentially loading said parallel/serial shift register means with an ''''0'''' when a pulse of width T1 is present and with a ''''1'''' when a pulse of width T2 is present.
Claim 5
Dependent Claim
52 words
The device as claimed in claim 2 wherein said pulse generating means comprises: a first and a second one-shot, the first one-shot being capable of generating a pulse of length T1 and the second one-shot capable of generating a pulse of length T2, said one-shots being coupled to said shift register means.
Claim 6
Dependent Claim
29 words
The device as claimed in claim 2 wherein said pulse generating means also provides a right shift in said parallel/serial shift register upon the presence of the T2 pulse.
Claim 7
Dependent Claim
29 words
The device as claimed in claim 2 wherein said pulse generating means gates the most significant bit of the serial word with the pulses of width T1 and T2.
Claim 8
Dependent Claim
28 words
The device as claimed in claim 2 wherein said comparing means includes a one-shot capable of providing a pulse of width T wherein T1 < T < T2.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |