Read-write random access memory system having single device memory cells with data refresh

Claim 2

A memory cell for use in a memory system in which a plurality of such cells are adapted to be arranged at a plurality of address stations in said system, said cell comprising a first switching device having first and second output terminals and a control terminal, means operatively connected to one of said output terminals for storing a data signal at one of two logic levels, a data output node connected to the other of said output terminals, and address selecting means selectively operatively connected to said control terminal and effective when present to actuate said switching device and operatively connect said first and second output terminals, thereby to transfer said data signal from said storing means to said output node, amplifier means having an input and an output, said input being operatively connected to said data output node, and a second switching device operatively interposed between said input and output, actuated by a timed signal, and effective when actuated to sense and refresh the signal on said data storing means.

Claim 3

The memory cell of claim 1, in which said amplifier means comprises a first signal source of a sense corresponding to but at a level greater than the level of one of said stored logic levels, and a second signal source of a reference signal corresponding to the other of said logic levels, means effective to initially charge said output to the level of said first signal, third switching means having a first output terminal operatively connected to said output, a second output terminAl operatively connected to said reference signal, and a control terminal operatively connected to said input and effective to actuate said third switching means when said stored logic level is at said other of its levels, thereby to charge said output to said reference signal.

Claim 4

The memory cell of claim 2, said amplifier means further comprising an intermediate node operatively connected to the control terminal of said third switching means, and means for establishing a bias level at said intermediate node at a value which is effective to normally deactuate said third switching means.

Claim 5

The memory cell of claim 3, further comprising a second intermediate node, fourth switching means having an output circuit operatively connected between said first mentioned intermediate node and said reference signal and a control terminal operatively connected to said second intermediate node, and capacitive feedback means operatively connected between said output and said second intermediate node.

Claim 6

The memory cell of claim 4, further comprising a third signal source corresponding in sense but of a lesser magnitude than said first-mentioned signal source, fifth switching means having an output circuit operatively connected to said third signal source and said first intermediate node and defining along with said fourth switching means said bias level establishing means.

Claim 7

The memory cell of claim 5, further comprising compensating means operatively connected to said second intermediate node and to said third signal source and effective to compensate for variations in the level of said third signal source, and to maintain the voltage at said second intermediate node substantially constant.

Claim 8

The memory cell of claim 6, said compensating means comprising sixth switching means having an output circuit operatively connected to said second intermediate node and a control terminal, a compensating node operatively connected to the control terminal of said sixth switching means, and means effective to establish a signal level thereat proportional to the level of said third signal.

Claim 9

The memory cell of claim 1, in which said first switching device is a field effect transistor having a gate defining said control terminal and a source and drain defining said output terminals, said data storing means comprising capacitance means.

Claim 10

The combination of claim 8, in which said amplifier means comprises a first signal source of a sense corresponding to but of a level greater than the level of one of said stored logic levels, and a second signal source of a reference signal corresponding to the other of said logic levels, means effective to initially charge said output to said first signal level, third switching means having a first output terminal operatively connected to said output, a second output terminal operatively connected to said reference signal, and a control terminal operatively connected to said input and effective to actuate said third switching means when said stored logic level is at said other of its levels, thereby to charge said output to said reference signal.

Claim 11

The combination of claim 9, said amplifier means further comprising an intermediate node operatively connected to the control terminal of said third switching means, and means for establishing a bias level at said intermediate node at a value which is effective to normally deactuate said third switching means.

Claim 12

The combination of claim 10, further comprising a second intermediate node, fourth switching means having an output circuit operatively connected between said first mentioned intermediate node and said reference signal and a control terminal operatively connected to said second intermediate node, and capacitive feedback means operatively connected between said output and said second intermediate node.

Claim 13

The combination of claim 11, further comprising a third signal source corresponding in sense but of a lesser magnitude than said first mentioned signal source, and fifth switchinG means having an output circuit operatively connected to said third signal source and said first intermediate node and defining along with said fourth switching means said bias level establishing means.

Claim 14

The combination of claim 12, further comprising compensating means operatively connected to said second intermediate node and to said third signal source and effective to compensate for variations in the level of said third signal source, and to maintain the voltage at said second intermediate node substantially constant.

Claim 15

The combination of claim 13, said compensating means comprising sixth switching means having an output circuit operatively connected to said second intermediate node and a control terminal, a compensating node operatively connected to the control terminal of said sixth switching means, and means effective to establish a signal level at said compensating node proportional to the level of said third signal.

Claim 16

A memory system comprising a plurality of memory cells arranged at the intersections of a plurality of intersecting rows and columns, each of said memory cells comprising a switching device having a control terminal and a normally open output circuit and data storing means operatively connected to one side of said output circuit for storing a data signal at one of two discrete logic levels, an output terminal, conductor means operatively connected to the other sides of the output circuits of all said switching devices in a given column, address selecting means including row and column select means, said row select means being operatively connected to said control terminal of said switching devices in the selected row of each of said columns and effective to close the output circuits of said devices in the selected row and to operatively apply the data signal from said data storing means to said conductor means, and first switching means effective when actuated to operatively connect a predetermined one of said conductor means to said output terminal, said column selecting means being effective to actuate said first switching means, thereby to operatively connect said conductor means in the selected column to said output terminal, and signal amplifier means having an input and an output, said input being operatively connected to said conductor means, and second switching means operatively interposed between said conductor means and said amplifier output, actuated by a timed signal, and effective when actuated to sense and refresh the voltage on said storing means.

Claim 17

A memory system comprising a plurality of memory cells arranged at the intersections of a plurality of intersecting rows and columns, each of said memory cells comprising a switching device having a control terminal and a normally open output circuit and data storing means operatively connected to one side of said output circuit for storing a data signal at one of two discrete logic levels, an output terminal, conductor means operatively connected to the other sides of the output circuits of all said switching devices in a given column, address selecting means including row and column select means, said row select means being operatively connected to said control terminal of said switching devices in the selected row of each of said columns and effective to close the output circuits of said devices in the selected row and to operatively apply the data signal from said data storing means to said conductor means, and first switching means effective when actuated to operatively connect a predetermined one of said conductor means to said output terminal, said column selecting means being effective to actuate said first switching means, thereby to operatively connect said conductor means in the selected column to said output terminal, and signal amplifier means having an input and an output, said input being operatively connected to said conductor means, and second switching means operatively interposed between said conductor means and said amplifier output, actuated by a timed signal, and effective when actuated to sense and refresh the voltage on said storing means.

Claim 18

The memory system of claim 15, in which said amplifier means comprises a first signal source of a sense corresponding to but at a level greater than the level of one of said stored logic levels, and a second signal source of a reference signal corresponding to the other of said logic levels, means effective to initially charge said output to the level of said first signal, third switching means having a first output terminal operatively connected to said output, a second output terminal operatively connected to said reference signal, and a control terminal operatively connected to said input and effective to actuate said third switching means when said stored logic level is at said other of its levels, thereby to charge said output to said reference signal.

Claim 19

The memory system of claim 16, said amplifier means further comprising an intermediate node operatively connected to the control terminal of said third switching means, and means for establishing a bias level at said intermediate node at a value which is effective to normally deactuate said third switching means.

Claim 20

The memory system of claim 17 further comprising a second intermediate node, fourth switching means having an output circuit operatively connected between said first mentioned intermediate node and said reference signal and a control terminal operatively connected to said second intermediate node, and capacitive feedback means operatively connected between said output and said second intermediate node.

Claim 21

The memory system of claim 18, further comprising a third signal source corresponding in sense but of a lesser magnitude than said first mentioned signal source, and fifth switching means having an output circuit operatively connected to said third signal source and said first intermediate node and defining along with said fourth switching means said bias level establishing means.

Claim 22

The memory system of claim 19, further comprising compensating means operatively connected to said second intermediate node and to said third signal source and effective to compensate for variations in the level of said third signal source, and to maintain the voltage at said second intermediate node substantially constant.

Claim 23

The memory system of claim 20, said compensating means comprising sixth switching means having an output circuit operatively connected to said second intermediate node and a control terminal, a compensating node operatively connected to the control terminal of said sixth switching means, and means effective to establish a signal level at said compensating node proportional to the level of said third signal.

Claim 24

A memory system comprising a memory cell comprising a switching device having a control terminal and a normally open output circuit and data storing means operatively connected to one side of said output circuit for storing a data signal at one of two discrete logic levels, a signal node operatively connected to the other side of said switching device output circuit, first control means operatively connected to said switching device control terminal and effective to cause said switching device output circuit to be closed, thereby to connect said data storing means to said signal node during first and second time intervals and to be open during a third time interval, all of said time intervals being substantially mutually exclusive, signal refreshing means, second control means operatively completing an operative connection from said signal node through said signal refreshing means and back to said signal node during said second time interval, an output terminal, third control means operatively completing an operative connection from said signal node to said output terminal during a time interval other than said first and second time intervals, biasing means, and fourth control means effective to operatively connect said biasing means to said signal node only during said third time interval.

Claim 25

A memory system comprising a memory cell comprising a switching device having a control terminal and a normally open output circuit and data storing means operatively connected to one side of said output circuit for storing a data signal at one of two discrete logic levels, a signal node operatively connected to the other side of said switching device output circuit, first control means operatively connected to said switching device control terminal and effective to cause said switching device output circuit to be closed, thereby to connect said data storing means to said signal node during first and second time intervals and to be open during a third time interval, all of said time intervals being substantially mutually exclusive, signal refreshing means, second control means operatively completing an operative connection from said signal node through said signal refreshing means and back to said signal node during said second time interval, an output terminal, third control means operatively completing an operative connection from said signal node to said output terminal during a time interval other than said first and second time intervals, biasing means, and fourth control means effective to operatively connect said biasing means to said signal node only during said third time interval.

Claim 26

The system of claim 22, in which said third control means is operative to complete its connection during said first time interval.

Claim 27

The system of claim 23, in which said third control means is operative to complete its connection substantially during both said first and second time intervals.