Accelerated bit-line discharge of a mosfet memory

Claim 1

A memory comprising: at least one storage cell constructed of MOS field effect transistors; a bit line connected to said storage cell and having a bit line capacitance which is discharged via said storage cell when one type of information is read; and a discharge circuit including a MOS field effect transistor switch having a controlled path connected between said bit line and a fixed potential and operable in response to discharging of said bit line capacitance via said storage cell to a predetermined voltage to conduct and speed the discharge of said bit line capacitance, said MOS field effect transistor switch of saiD discharge circuit being part of a bistable circuit including first and second MOS field effect transistors having respective controlled conduction paths and connected as a bistable circuit, and a third MOS field effect transistor connected as a load transistor connecting the controlled conduction path of said first MOS transistor to another fixed potential, said second MOS transistor having its controlled conduction path connected to said bit line, said first MOS transistor having a control input also connected to said bit line, and said second MOS transistor having a control input also connected to the other fixed potential via said third MOS transistor.