Method of and apparatus for code detection

Claim 3

decoding each group of N consecutively received bits;

Claim 4

decoding each group of N consecutively received bits;

Claim 5

a sub-pattern counter register for counting registration of a sub-pattern in said detection register; and

Claim 6

a sub-pattern counter register for counting registration of a sub-pattern in said detection register; and

Claim 7

A communication system for transmitting both data representative of a special important condition and normal data over the same communication path, which communication system includes a transmitter for generating a bit serial bit stream pattern representative of a special condition, which pattern comprises M sub-patterns each of which are N bits long and each of which comprises N-1 bits of a first state and one bit of a second state, wherein M and N are both integer numbers and M is at least 2, comprising in combination:

Claim 8

A communication system for transmitting both data representative of a special important condition and normal data over the same communication path, which communication system includes a transmitter for generating a bit serial bit stream pattern representative of a special condition, which pattern comprises M sub-patterns each of which are N bits long and each of which comprises N-1 bits of a first state and one bit of a second state, wherein M and N are both integer numbers and M is at least 2, comprising in combination:

Claim 9

A receiver for receiving both important data representative of a special condition and normal data from the same communication path, comprising, in combination: A. normal data receiving means for bit serially receiving a bit stream of data from a data path, and for responding to a said bit stream corresponding to normal data; and B. special condition data receiving means for receiving a bit stream of data from said data path and for producing a signal representative of a special condition in response to a said bit stream of a pattern which comprises M sub-patterns each of which are N bits long and each of which comprises N-1 consecutive bits of a first state and one bit of a second state, wherein M and N are integer numbers and M is at least 2, wherein said special condition data receiving means includes a sub-pattern detection register for bit-serially registering N consecutively received bits of a bit stream and for providing a first output representative of the state of the Nth bit of said N bits and for providing a second output representative of the collective output of the other N-1 registered bits, which collective output is a said first state when said N-1 registered bits all are a first state and is a second state when any one of said N-1 registered bits is a second state; a sub-pattern counter register for counting a registration of a said sub-pattern in said detection register; and a register control means coupled to said detection register for decoding said detection reGister outputs and for updating said counter register when said outputs are anticoincident with said first output of a second state and said second output of a first state; and for clearing both said detection and said counter registers in response to decoding both said outputs as a first state and for clearing said counter register in response to decoding both said outputs as a second state.

Claim 10

A receiver for receiving both important data representative of a special condition and normal data from the same communication path, comprising, in combination: A. normal data receiving means for bit serially receiving a bit stream of data from a data path, and for responding to a said bit stream corresponding to normal data; and B. special condition data receiving means for receiving a bit stream of data from said data path and for producing a signal representative of a special condition in response to a said bit stream of a pattern which comprises M sub-patterns each of which are N bits long and each of which comprises N-1 consecutive bits of a first state and one bit of a second state, wherein M and N are integer numbers and M is at least 2, wherein said special condition data receiving means includes a sub-pattern detection register for bit-serially registering N consecutively received bits of a bit stream and for providing a first output representative of the state of the Nth bit of said N bits and for providing a second output representative of the collective output of the other N-1 registered bits, which collective output is a said first state when said N-1 registered bits all are a first state and is a second state when any one of said N-1 registered bits is a second state; a sub-pattern counter register for counting a registration of a said sub-pattern in said detection register; and a register control means coupled to said detection register for decoding said detection reGister outputs and for updating said counter register when said outputs are anticoincident with said first output of a second state and said second output of a first state; and for clearing both said detection and said counter registers in response to decoding both said outputs as a first state and for clearing said counter register in response to decoding both said outputs as a second state.

Claim 11

register control means coupled to said detection register for decoding the N bits registered in said sub-pattern detection register, which register control means is responsive to decoding registration of a said sub-pattern by said detection register to update the count of said counter register, is responsive N bit times subsequent to a said decoding of a registration to update and to clear said sub-pattern counter for decodings, respective, corresponding to and inconsistent with a sub-pattern, and is responsive to a decoding corresponding to a said sub-pattern at an interval less than N bit times subsequent to a prior decoding of a sub-pattern registration to clear said sub-pattern counter register.

Claim 12

register control means coupled to said detection register for decoding the N bits registered in said sub-pattern detection register, which register control means is responsive to decoding registration of a said sub-pattern by said detection register to update the count of said counter register, is responsive N bit times subsequent to a said decoding of a registration to update and to clear said sub-pattern counter for decodings, respective, corresponding to and inconsistent with a sub-pattern, and is responsive to a decoding corresponding to a said sub-pattern at an interval less than N bit times subsequent to a prior decoding of a sub-pattern registration to clear said sub-pattern counter register.

Claim 13

updating a sub-pattern counter in response to decoding a said group of bits corresponding to a sub-pattern and in response to decoding a said group of bits corresponding to a sub-pattern at an interval of N bit times subsequent to a prior decoding of a said sub-pattern.

Claim 14

updating a sub-pattern counter in response to decoding a said group of bits corresponding to a sub-pattern and in response to decoding a said group of bits corresponding to a sub-pattern at an interval of N bit times subsequent to a prior decoding of a said sub-pattern.

Claim 15

clearing said sub-pattern counter in response to decoding a said group of bits inconsistent with a sub-pattern at an interval N bit times subsequent to decoding a said group of bits corresponding to a sub-pattern and in response to decoding a said group of bits corresponding to a sub-pattern at an interval less than N bit times subsequent to a prior decoding of a said group of bits corresponding to a sub-pattern.

Claim 16

clearing said sub-pattern counter in response to decoding a said group of bits inconsistent with a sub-pattern at an interval N bit times subsequent to decoding a said group of bits corresponding to a sub-pattern and in response to decoding a said group of bits corresponding to a sub-pattern at an interval less than N bit times subsequent to a prior decoding of a said group of bits corresponding to a sub-pattern.

Claim 17

A receiver according to claim 3 wherein said detection register comprises an N-1 count ring counter for registering said preceding N-1 bits and means for providing said data line state as said first output for registering said nth bit.

Claim 18

A receiver according to claim 4 wherein said detection register comprises an n bit shift register and said first output comprises the least significant bit of the shift register and said second output comprises the most significant bit of the shift register.

Claim 19

A receiver according to claim 3 wherein said special condition receiving means includes a sub-pattern detection register which registers the Nth bit of a sub-pattern as the state of said data path and having a sub-pattern detection counter having a length of N-1 bits and which updates its count in response to a said first state signal from said data path but clears its count in response to a second state signal from said data path whereby said special condition receiving means is responsive to a second state synchronization bit followed by M said sub-patterns to provide said signal representative of a special condition; and a sub-pattern counter responsive to the combination of a full-count of said detection register counter and an Nth bit registration of a second state to update its count.

Claim 20

A receiver according to claim 6 wherein said sub-pattern detection counter provides indications of N registered bits by providing a first output representative of the state of the Nth bit and a second output representative of the collective state of N-1 consecutive bits and further comprises control means responsive to a combination of a first output representative of said Nth bit having a second state and said N-1 consecutive bits having a second state to apply a clear signal to said sub-pattern detection register counter.

Claim 21

A receiver according to claim 6 wherein said control means is responsive to the combination of said first output and said second output both of a first state, to clear both said detection register counter and said sub-pattern counter.