Patent US3764920A successfully refreshed from Google Patents.
US3764920A
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US
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Apparatus for sampling an asynchronous signal by a synchronous signal
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1972-06-15
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Granted: 1973-10-09
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Expires: 1992-06-15
Abstract
Abstract The asynchronous signal is complemented and directed to a latching logic circuit as the data input and the synchronous signal are directed to the clock input of the latching circuit. The latching circuit has built-in delays to reliably latch if the low or active portion of the asynchronous pulse occurs during the ''''window'''' or high portion of the synchronous signal. The latching circuit also includes a jamming circuit connected to its clock input whereby a low or disabled window time of the synchronous signal prevents a change in state by the latching circuit. A pulse delay circuit generates a sampling pulse a period of time after the window time to sample the output of the latching circuit.
Inventors
- 👤 A Galcik
- 👤 R Lange
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:28
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K3/00; H03K3/02; H03K3/027
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
300 words
A system for sampling an asynchronous signal by a synchronous signal comprising: a latching device having a data input terminal, a clock input terminal, and an output terminal; the synchronous signal directed to the clock input terminal of the latching device and having its positive portion as a sampling window; the asynchronous signal directed to the data input terminal of the latching circuit and having its negative portion as an actuation period; said latching device including a jamming circuit connected to the clock and data input terminals for generating a jamming signal upon the inclusive occurrence of either or both positive asynchronous signals or negative synchronous signals, a feedback latching circuit for generating feedback latching signals and for generating output signals onto the output terminal, and logic circuitry means for emitting a first signal upon the concurrent occurrence of positive synchronous and asynchronous signals, a second signal upon the concurrent occurrence of positive feedback and jamming signals and a third signal upon the inclusive occurrence of either or both positive first signals or positive second signals; said feedback latching circuit activated by said third signal to generate the output signal and to generate the feedback latching signal after a time delay; a pluse delay circuit having its input terminal connected to the synchronous signal and actuated by a positive to negative excursion of the synchronous signal for providing a sampling signal on its output terminal after a period of time; and a logic gate having one input terminal connected to the output terminal of said pulse delay circuit and a second input terminal connected to the output terminal of said latching circuit to provide an output signal when the sampling signal occurs concurrently with the actuation of the latching circuit output by the positive synchronous signal and negative asynchronous signal.
Claim 2
Independent Claim
300 words
A system for sampling an asynchronous signal by a synchronous signal comprising: a latching device having a data input terminal, a clock input terminal, and an output terminal; the synchronous signal directed to the clock input terminal of the latching device and having its positive portion as a sampling window; the asynchronous signal directed to the data input terminal of the latching circuit and having its negative portion as an actuation period; said latching device including a jamming circuit connected to the clock and data input terminals for generating a jamming signal upon the inclusive occurrence of either or both positive asynchronous signals or negative synchronous signals, a feedback latching circuit for generating feedback latching signals and for generating output signals onto the output terminal, and logic circuitry means for emitting a first signal upon the concurrent occurrence of positive synchronous and asynchronous signals, a second signal upon the concurrent occurrence of positive feedback and jamming signals and a third signal upon the inclusive occurrence of either or both positive first signals or positive second signals; said feedback latching circuit activated by said third signal to generate the output signal and to generate the feedback latching signal after a time delay; a pluse delay circuit having its input terminal connected to the synchronous signal and actuated by a positive to negative excursion of the synchronous signal for providing a sampling signal on its output terminal after a period of time; and a logic gate having one input terminal connected to the output terminal of said pulse delay circuit and a second input terminal connected to the output terminal of said latching circuit to provide an output signal when the sampling signal occurs concurrently with the actuation of the latching circuit output by the positive synchronous signal and negative asynchronous signal.
Claim 3
Dependent Claim
137 words
A system according to claim 1 wherein said latching device includes: a first AND-gate havIng an input connected to the data terminal and an input connected to the clock terminal; a first OR-gate logic circuit having one input connected to the data terminal; an inverter connected between the clock terminal and a second input of said first OR-gate; a second AND-gate having its inputs connected to the output of said first OR-gate and to the delayed feedback latching signal; a second OR-gate having its inputs connected to the outputs of said first and second AND-gates; a second inverter connected between the output of said second OR-gate and the output terminal of the latching circuit; and a third inverter connected to the output terminal for generating the delayed feedback latching signal to the input to the second AND-gate.
Claim 4
Dependent Claim
48 words
A system according to claim 1 wherein the jamming circuit comprises: a first OR-gate having one input connected to the data input terminal; and a first inverter having its input connected to the clock input terminal and its output connected to a second input of the first OR-gate.
Claim 5
Dependent Claim
76 words
A system according to claim 1 wherein the feedback latching circuit comprises: a second and a third inverter connected in series; and a first AND-gate having one input connected to the output of the jamming circuit and a second input connected to the output of the third inverter; wherein the input to the second inverter comprises the alternative of the concurrent occurrence of the positive asynchronous and synchronous signals, and the output of the first AND-gate.
Claim 6
Dependent Claim
241 words
A latching logic system comprising: a latching circuit having a data and a clock input terminal and an output terminal; an asynchronous signal directed to the data input terminal of the latching circuit; a synchronous signal directed to the clock input terminal of the latching circuit; said latching circuit being activated to change its state to generate an activated latch signal by the concurrent occurrence of the positive portion of the synchronous signal and a negative portion of the asynchronous signal; a pulse delay circuit generating a sampling signal in response to said synchronous signal; and an output logic gate generating an output signal upon the concurrent occurrence of the sampling signal and the activated latch signal; said latching circuit including; a first AND-gate having its inputs connected to the data and clock terminals; a first OR-gate logic circuit having one input connected to the data terminal; an inverter connected between the clock terminal and a second input of said first OR-gate; a second AND-gate having its inputs connected to the output of said first OR-gate and to the delayed feedback latching signal; a second OR-gate having its inputs connected to the outputs of said first and second AND-gates; a second inverter connected between the output of said second OR-gate and the output terminal of the latching circuit; and a third inverter connected to the output terminal for generating the delayed feedback latching signal to the input to the second AND-gate.
Claim 7
Dependent Claim
241 words
A latching logic system comprising: a latching circuit having a data and a clock input terminal and an output terminal; an asynchronous signal directed to the data input terminal of the latching circuit; a synchronous signal directed to the clock input terminal of the latching circuit; said latching circuit being activated to change its state to generate an activated latch signal by the concurrent occurrence of the positive portion of the synchronous signal and a negative portion of the asynchronous signal; a pulse delay circuit generating a sampling signal in response to said synchronous signal; and an output logic gate generating an output signal upon the concurrent occurrence of the sampling signal and the activated latch signal; said latching circuit including; a first AND-gate having its inputs connected to the data and clock terminals; a first OR-gate logic circuit having one input connected to the data terminal; an inverter connected between the clock terminal and a second input of said first OR-gate; a second AND-gate having its inputs connected to the output of said first OR-gate and to the delayed feedback latching signal; a second OR-gate having its inputs connected to the outputs of said first and second AND-gates; a second inverter connected between the output of said second OR-gate and the output terminal of the latching circuit; and a third inverter connected to the output terminal for generating the delayed feedback latching signal to the input to the second AND-gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |