US3764919A
Expired / Lapsed
US
⏱️ 0.0 years remaining
An n-ary of flip-flop cells interconnected by rows of logic gates
Assignee: SHINTRON CO Inc
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Filing: 1972-12-22
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Granted: 1973-10-09
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Expires: 1992-12-22
Abstract
Abstract A n-ary flip-flop is constructed of a series of binary cells interconnected by two rows of logic gates. One row of logic gates provides a signal to a selected ''''set'''' cell when all cells to the left of the selected cell are reset and the other row of logic gates provides a signal to the selected cell when all cells to its right are in the reset state. The logic gate signals hold the selected cell in the ''''on'''' state after the original SET signal has decayed. When a different cell is placed in the set state, one row of logic gates propagates a signal to the right of that cell to reset all gates to the right while the other row concurrently propagates a signal in the other direction to reset all gates to the left. The n-ary flip-flop is modularly expandable inasmuch as cells can be readily added to both ends of the series of cells merely by connecting each added cell to the two rows of logic gates.
Inventors
- 👤 L Baxter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:34
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/038; H03K21/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
270 words
An n-ary flip-flop comprising n cells, each cell having two stable states and reSiding in one or the other of those states except when in transition from one state to the other, the cells being arranged in series, a first row of gates for propagating a signal in one direction along the serially arranged cells, each gate in the first row being associated with a different cell and receiving an input from that cell, each gate having its output connected to an input of the next succeeding gate in the row and to an input of the cell associated with that next gate whereby when a cell is placed in one stable state, its associated first row gate causes a signal to propagate along the row in said one direction which causes the other cells in that direction to remain in or be reset to the other stable state, a second row of gates for propagating a signal along the serially arranged cells in the direction opposite to said one direction, each gate in the second row being associated with a different cell and receiving an input from that cell, each gate of the second row having its output connected to an input of the next succeeding gate in that row and to an input of the cell associated with that next gate whereby when a cell is placed in said one stable state, its associated second row gate causes a signal to propagate along that row in said opposite direction which causes the other cells in that direction to remain in or be reset to the other stable state.
Claim 2
Dependent Claim
270 words
An n-ary flip-flop comprising n cells, each cell having two stable states and reSiding in one or the other of those states except when in transition from one state to the other, the cells being arranged in series, a first row of gates for propagating a signal in one direction along the serially arranged cells, each gate in the first row being associated with a different cell and receiving an input from that cell, each gate having its output connected to an input of the next succeeding gate in the row and to an input of the cell associated with that next gate whereby when a cell is placed in one stable state, its associated first row gate causes a signal to propagate along the row in said one direction which causes the other cells in that direction to remain in or be reset to the other stable state, a second row of gates for propagating a signal along the serially arranged cells in the direction opposite to said one direction, each gate in the second row being associated with a different cell and receiving an input from that cell, each gate of the second row having its output connected to an input of the next succeeding gate in that row and to an input of the cell associated with that next gate whereby when a cell is placed in said one stable state, its associated second row gate causes a signal to propagate along that row in said opposite direction which causes the other cells in that direction to remain in or be reset to the other stable state.
Claim 3
Dependent Claim
47 words
The n-ary flip-flop according to claim 1 wherein the first and second rows of gates apply signals to the cell placed in said one stable state which holds that cell in said one stable state when all the other cells are reset to the other stable state.
Claim 4
Dependent Claim
33 words
The n-ary flip-flop according to claim 2 wherein each cell has an input terminal through which a signal can be applied to cause the cell to be set in said one stable state.
Claim 5
Dependent Claim
101 words
The n-ary flip-flop according to claim 1 wherein each cell has an input terminal through which a signal can be applied to cause the cell to be set in said one stable state, signal transfer means coupling the output of each preceding cell in the series to the input terminal of the next succeeding cell in the series whereby the succeeding cell can be placed in said one stable state by a signal from the preceding cell, and a source of clock pulses connected to the first row of gates for causing reset signals to propagate along that row of gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |