Phasemeter employing means for preventing errors in the phase reading produced by noise

Claim 2

Apparatus for measuring the phase difference between two incoming AC signals comprising a phase detector operable in either of two operating states in response to applied signals; means coupled to said phase detector and responsive to each zero crossing in at least one direction of one incoming AC signal for producing a first transistion of said phase detector to a first state, means coupled to said phase detector and responsive to each zero crossing in at least one direction of the other incoming AC signal for producing a second transition of said phase detector to a second state, the interval between said two Transitions providing a measure of the phase difference between the two incoming signals and multiple zero crossings of one of said incoming signals at times within the interval between zero crossings of the other of said incoming signals producing an undesired transition of said phase detector to an incorrect state, means coupled to said phase detector for detecting the incorrect state of said phase detector, and means responsive to said detecting means for changing the state of said phase detector to the correct state.

Claim 3

Apparatus as claimed in claim 1 including means for converting said two incoming AC signals to square wave signals, each having a first state and a second state, and said means for detecting the incorrect state of said phase detector comprising logic circuit means for detecting the instantaneous states of said two square waves and said phase detector.

Claim 4

Apparatus for measuring the phase difference between two incoming AC signals comprising first and second logic means, each operative in either one of two logic states in response to an applied signal, means for converting said two incoming AC signals to resultant signals, each having a first and second discrete logic state, means coupled to said logic means and responsive to the opposite zero crossings of one resultant signal for producing a first transition of said first logic means to a first state and a first transition of said second logic means to a first state, respectively, means coupled to said logic means and responsive to the opposite zero crossings of the other resultant signal for producing a second transition of said first logic means to a second state and a second transition of said second logic means to a second state, respectively, the time intervals of said first and second logic means in one of said states of each logic means providing an indication of the phase difference between the two incoming signals and multiple zero crossings of one of said resultant signals at times within the interval between zero crossings of the other of said resultant signals producing an undesired transition of one of said logic means to an incorrect state, circuit means for detecting the instantaneous logic states of said two resultant signals and of said two logic means for producing a correction signal therefrom, and means responsive to said correction signal for changing the logic state of one logic means operating in an incorrect state to the correct state.

Claim 5

Apparatus for measuring the phase difference between two incoming AC signals comprising first and second logic means, each operative in either one of two logic states in response to an applied signal, means for converting said two incoming AC signals to resultant signals, each having a first and second discrete logic state, means coupled to said logic means and responsive to the opposite zero crossings of one resultant signal for producing a first transition of said first logic means to a first state and a first transition of said second logic means to a first state, respectively, means coupled to said logic means and responsive to the opposite zero crossings of the other resultant signal for producing a second transition of said first logic means to a second state and a second transition of said second logic means to a second state, respectively, the time intervals of said first and second logic means in one of said states of each logic means providing an indication of the phase difference between the two incoming signals and multiple zero crossings of one of said resultant signals at times within the interval between zero crossings of the other of said resultant signals producing an undesired transition of one of said logic means to an incorrect state, circuit means for detecting the instantaneous logic states of said two resultant signals and of said two logic means for producing a correction signal therefrom, and means responsive to said correction signal for changing the logic state of one logic means operating in an incorrect state to the correct state.

Claim 8

The method as claimed in claim 4 including the step of converting each of said two incoming signals to a related signal having a different state for each half cycle of the incoming signal, and wherein said step of sensing said incorrect state comprises sensing the instantaneous states of said two related signals and said trigger circuit and producing an error correction signal therefrom to change the state of said trigger circuit from the incorrect to the correct state.

Claim 11

The method as claimed in claim 6 including the step of converting each of said two incoming signals to a related signal, each related signal having a different state for each half cycle of the associated incoming signal, and wherein said step of sensing said incorrect state comprises sensing the instantaneous states of said two related signals and said two trigger circuits and producing an error correction signal therefrom to change the state of said trigger circuit from the incorrect to the correct state.