US3629712A
Expired / Lapsed
US
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Phase comparator
Assignee: TDK Micronas GmbH
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Filing: 1970-08-24
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Granted: 1971-12-21
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Expires: 1990-08-24
Abstract
Abstract An improved phase comparator for a phase-locked loop to extract the bit clock from binary data bits by detecting both the positive and negative transitions of the data bits. An equal number of the positive and negative transitions, statistically, are sampled and a transition (either positive or negative) is inhibited by cooperation of an additional bistable device controlled by a monostable device, if this transition occurs within one bit period after a previously sampled transition (either positive or negative). This technique compensates for the asymmetrical phase noise characteristic present due to transition jitter when only one transition of the data bits are detected and prevents an attempt at 100 percent duty cycle operation of the monostable device when both transitions of the data bits are detected.
Inventors
- 👤 James M Clark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:33
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
224 words
A system to generate an output signal indicative of the phase relationship of a first pulse signal and a second pulse signal, each pulse of said first pulse signal having a width equal to an integral multiple of a predetermined width, wherein said integral includes one, and each pulse of said second pulse signal having a width less than one-half said predetermined width and a repetition period equal to said predetermined width, comprising: a first source of said first pulse signal, said first signal is a binary intelligence signal having a bit period equal to said predetermined width; first means coupled to said first source to produce a third pulse signal including a pulse having a width less than onehalf said predetermined width corresponding to each transition of each of the pulses of said first pulse signal; a second source of said second pulse signal, said second signal is produced to indicate a given on of the transitions of a local bit clock signal which is to be synchronized with the bits of said binary intelligence signal; second means coupled to said first means and said second source to produce a fourth pulse signal having adjacent pulses therein separated by an amount greater than said predetermined width; and third means coupled to said second means and said second source to produce said output signal.
Claim 2
Independent Claim
224 words
A system to generate an output signal indicative of the phase relationship of a first pulse signal and a second pulse signal, each pulse of said first pulse signal having a width equal to an integral multiple of a predetermined width, wherein said integral includes one, and each pulse of said second pulse signal having a width less than one-half said predetermined width and a repetition period equal to said predetermined width, comprising: a first source of said first pulse signal, said first signal is a binary intelligence signal having a bit period equal to said predetermined width; first means coupled to said first source to produce a third pulse signal including a pulse having a width less than onehalf said predetermined width corresponding to each transition of each of the pulses of said first pulse signal; a second source of said second pulse signal, said second signal is produced to indicate a given on of the transitions of a local bit clock signal which is to be synchronized with the bits of said binary intelligence signal; second means coupled to said first means and said second source to produce a fourth pulse signal having adjacent pulses therein separated by an amount greater than said predetermined width; and third means coupled to said second means and said second source to produce said output signal.
Claim 3
Dependent Claim
96 words
A system according to claim 1, wherein said second source includes at least a third source of pulse signal, each pulse thereof having a width equal to one-half said predetermined width And a repetition period equal to said predetermined width, a delay device coupled to said third source, a NOT circuit coupled to the output of said delay device, and a two input NAND gate having one input coupled to said third source and the other input coupled to the output of said NOT circuit, the output of said NAND gate providing said second pulse signal.
Claim 4
Dependent Claim
147 words
A system according to claim 1, wherein said first means includes at least a first NOT circuit coupled to said first source, a delay device coupled to the output of said first NOT circuit, a second NOT circuit coupled to the output of said delay device, a first two input NAND gate having one input coupled to said first source and the other input coupled to the output of said delay device, a second two input NAND gate having one input coupled to the output of said first NOT circuit and the other input coupled to the output of said second NOT circuit, and a third two input NAND gate having one input coupled to the output of said first NAND gate and the other input coupled to the output of said second NAND gate, the output of said third NAND gate providing said third pulse signal.
Claim 5
Dependent Claim
141 words
A system according to claim 1, wherein said second means includes a bistable device having a set input, a reset input and two outputs, said reset input being coupled to said second source, a two input NAND gate having one input couplet to the output of said first means and the other input coupled to one of the outputs of said bistable device, the output of said NAND gate providing said fourth pulse signal, and a monostable device having its input coupled to the output of said NAND gate and its output coupled to said set input of said bistable device, the width of the pulse produced by said monostable device being equal to said predetermined width to inhibit pulses of said third pulse signal occurring less than said predetermined width after the immediately preceding pulse of said third pulse signal.
Claim 6
Dependent Claim
63 words
A system according to claim 1, wherein said third means includes a bistable device having a set input, a reset input and two outputs, said reset input being coupled to said second source and said set input being coupled to the output of said second means, and means coupled to one of said outputs of said bistable device to produce said output signal.
Claim 7
Dependent Claim
508 words
A system according to claim 1, wherein said second source includes at least a third source of pulse signal, each pulse thereof having a width equal to one-half said predetermined width and a repetition period equal to said predetermined width, a first delay device coupled to said third source, a first NOT circuit coupled to the output of said first delay device, and a first two input NAND gate having one input coupled to said third source and the other input coupled to the output of said first NOT circuit, the output of said first NAND gate providing said second pulse signal; said first means includes at least a second NOT circuit coupled to said first source, a second delay device coupled to the output of said second NOT circuit, a third NOT circuit coupled to the output of said second delay device, a second two input NAND gate having one input coupled to said first source and the other input coupled to the output of said second delay device, a third two input NAND gate having one input coupled to the output of said second NOT circuit and the other input coupled to the output of said third NOt circuit, and a fourth two input NAND gate having one input coupled to the output of said second NAND gate and the other input coupled to the output of said third NAND gate, the output of said fourth NAND gate providing said third pulse signal; said second means includes a first bistable device having a set input, a reset input and two outputs, said reset input being coupled to the output of said first NAND gate, a fifth two input NAND gate having one input coupled to the output of said fourth NAND gate and the other input coupled to one of the outputs of said first bistable device, the output of said fifth NAND gate providing said fourth pulse signal, and a monostable device having its input coupled to the output of said fifth NAND gate and its output coupled to said set input of said first bistable device, the width of the pulse produced by said monostable device being equal to said predetermined width to inhibit pulses of said third pulse signal occurring less than said predetermined width after the immediately preceding pulse of said third pulse signal; and said third means includes a second bistable device having a set input, a reset input and two outputs, said reset input being coupled to the output of said first NAND gate and said set input being coupled to the output of said fifth NAND gate, a fourth NOT circuit coupled to one of the outputs of said second bistable device, a sixth two input NAND gate having one input coupled to said one of the outputs of said second bistable device and the other input coupled to the output of said monostable device, and means coupled to the output of said fourth NOT circuit and the output of said sixth NAND gate to produce said output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-20 | 1975-06-21 | 1975-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-20 | 1979-06-21 | 1979-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-20 | 1983-06-21 | 1983-12-21 | $7700.00 | Window Closed / Lapsed |