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Patent US3764788A successfully refreshed from Google Patents.
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US3764788A Expired / Lapsed US ⏱️ 0.0 years remaining

Error checking circuit

Assignee: International Business Machines Corp
•
Filing: 1972-06-30
•
Granted: 1973-10-09
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Expires: 1992-06-30
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Abstract

Abstract A new circuit is provided for checking for errors caused by most but not all of the faults that might occur in a network of logic gates. One part of the checking circuits, called a ''''1 cover'''' produces an output that is designated C1, and includes selected prime implicants of the function, F, of the newtork being checked. Thus, if there is no fault in either the circuit being checked or in the 1 cover circuit, C1 1 implies that F 1. A comparison circuit is provided to produce an error signifying output, E, for the condition C1 1 and F 0. Similarly, another part of the checking circuit, called a ''''0 cover'''' produces an output that is designated CO and includes selected prime implicants of the complement, F, of the circuit being checked. The comparison part of the checking circuit detects the condition CO 1, F 0, as an error condition. Thus, the checking circuit of this invention operates according to the equation E FCO + FC1. The circuit responds to a high portion of the possible faults in the circuit being checked but it has many fewer components than the circuit being checked.

Inventors

  • 👤 S Hong
  • 👤 D Jones
  • 👤 D Ostapko

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 13:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 95 words
A checking circuit for a network of interconnected logic gates having as an output a function F of inputs x1x2. . .xn, comprising, first logic means connected to form an output function C1 composed of selected prime implicants of said function F, second logic means connected to form an output function C0 composed of selected prime implicants of the complement F of said function F, and third logic means connected to receive said functions F, F, C0 and C1 and to produce an error signifying output E accordIng to the relationship E FC0 + FC1.
Claim 2
Dependent Claim 95 words
A checking circuit for a network of interconnected logic gates having as an output a function F of inputs x1x2. . .xn, comprising, first logic means connected to form an output function C1 composed of selected prime implicants of said function F, second logic means connected to form an output function C0 composed of selected prime implicants of the complement F of said function F, and third logic means connected to receive said functions F, F, C0 and C1 and to produce an error signifying output E accordIng to the relationship E FC0 + FC1.
Claim 3
Dependent Claim 97 words
The checking circuit of claim 1 wherein a fault in the network to be checked is defined as a stuck 1 or a stuck 0 at one of a predetermined number of check points in the network to be checked and said first and second logic means are a 1 cover circuit and a 0 cover circuit respectively, and said cover circuits include means to produce a first prime implicant that covers a largest number of said faults and a second prime implicant that covers a largest number of faults not covered by said first prime implicant.
Claim 4
Dependent Claim 35 words
The checking circuit of claim 2 wherein one of said cover circuits includes means to produce said first prime implicant and the other of said cover circuits includes means to produce said second prime implicant.
Claim 5
Dependent Claim 28 words
The checking circuit of claim 3 wherein the cover circuits include logic gates to produce a number of said prime implicants covering about 90 percent of said faults.
Claim 6
Dependent Claim 24 words
The checking circuit of claim 4 wherein said cover circuits include not more than 30 percent as many gates as the network being checked.
Claim 7
Dependent Claim 24 words
The checking circuit of claim 2 wherein at least one of the prime implicants of C1 is not a minimum sum term of F.
Claim 8
Dependent Claim 24 words
The checking circuit of claim 6 wherein one of said cover circuits produces a prime implicant that is a minimum sum term of F.
Claim 9
Dependent Claim 24 words
The checking circuit of claim 6 wherein one of said cover circuits produces a prime implicant that is a minimum sum term of F.
Claim 10
Dependent Claim 27 words
The checking circuit of claim 2 wherein at least one of said prime implicants does not appear at any discrete point in the network to be checked.
Claim 11
Dependent Claim 14 words
The checking circuit of claim 2 including means producing a corrected function F(corrected) FVEV(C0C1).

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-10-08 1977-04-09 1977-10-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-10-08 1981-04-09 1981-10-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-10-08 1985-04-09 1985-10-09 $7700.00 Window Closed / Lapsed

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