Multi-speed digital to synchro converters

Claim 2

A digital to analog converter comprising counting means, an impedance ladder network, gating means for selectively connecting inputs to said network corresponding to both the number registered in said counting means and the complement thereof, and means for producing a voltage corresponding to the sine of the voltage produced by said network.

Claim 3

A digital to analog converter as defined in claim 1, including a second impedance ladder network, second gating means for selectively connecting inputs to said network corresponding to both the number registered in said counting means and the complement thereof, means for producing a voltage and corresponding to the sine of the voltage produced by said second network, and means whereby the number in said counting means is gated to the first network when the complement of said number is gated to said second network, and vice versa.

Claim 4

A digital to analog converter as defined in claim 1, wherein said counting means comprises a plurality of N binary stages each having complementary outputs representing the state of the stage, said gating means being connected to produce an output representing the number stored in the first (N minus 1) stages when said N stage is in a first condition, and operative to produce an output corresponding to the complement of the numbers stored in said first (N minus 1) stages when said N stage is in the other condition.

Claim 5

A digital to analog converter as defined in claim 2, wherein said counting means comprises a plurality of N binary stages each having complementary outputs representing the state of the stage, the first mentioned gating means being connected to produce an output representing the number stored in the first (N minus 1) stages when said N stage is in a first condition, and operative to produce an output corresponding to the complement of the numbers stored in said first (N minus 1) stages when said N stage is in the other condition, and said second gating means being connected to produce an output representing the number stored in the first (N minus 1) stages when said N stage is in said other condition, and operative to produce an output corresponding to the complement of the numbers stored in said first (N minus 1) stages when said N stage is in said first condition.

Claim 6

A digital to analog converter according to claim 1 including a second impedance ladder network and second gating means for selectively connecting inputs to said second network, corresponding to both the number registered in said counting means and the complement thereof, and second means for producing a voltage corresponding to the sine of the voltage produced by said second network, a plurality of consecutive intermediate stages of counting means being connected through both said first and said second gating means, whereby said intermediate stages function as the most significant stages of a fine resolution counting means and as the least significant stages of a coarse resolution counting means.

Claim 7

A digital to analog converter according to claim 1 comprising second counting means, a second impedance ladder network, and second gating means for selectively connecting inputs to said second network, corresponding to both the number registered in said counting means and the complement thereof, a plurality of consecutive stages of the first mentioned counting means representing the least significant data therein, being identical to a corresponding plurality of consecutive stages in the second counting means, corresponding to the most significant data therein, whereby said plurality of stages are connected in common to both the first mentioned gating means and said second gating means.

Claim 8

A digital to analog converter as defIned in claim 5, including corresponding third and fourth gating means interconnected with third and fourth impedance ladder networks and respective means for producing voltages corresponding to the sine of the voltages produced by said third and fourth networks, the outputs of said first mentioned network and said second network being connected to drive a coarse synchro and fine synchro respectively and the outputs of said third and fourth networks being operative to drive a second coarse synchro and second fine synchro respectively, said coarse synchro and said fine synchro being 90* out of phase with said second coarse synchro and said second fine synchro.

Claim 9

A digital to analog converter as defined in claim 1, including storage means operative to store a signal corresponding to the output of said last mentioned means, and means operative to successively store data in said counting means and initiate a count cycle thereof.