Semiconductor device for scanning digital signals

Claim 2

A semiconductor scanning device comprising: a row of plurality of metal-oxide-semiconductor field effect transistors, each transistor having a source, a gate and a drain region and a respective electrode connected thereto, disposed with substantially the same distance between each field effect transistor on one surface of a semiconductor substrate, with the respective gate threshold voltages of said transistor substantially linearly increasing with distance from the lowest level at the transistor at one end of said row to the highest level at the transistor at the other end of said row; first means for successively electrically interconnecting the gate electrodes of each of said transistors along said row; second means, connected to the respective source and drain electrodes of each transistor, for supplying electric current thereto; and third means, connected to the interconnected gate electrodes of each of said transistors, for applying pulses of a saw-tooth waveform thereto, the height of said waveform varying in a substantially linear manner between a maximum value and a minimum value with respect to time, said maximum value being of a first sufficient magnitude to permit current flow between the source and drain electrode of the transistor at said other end of said row, and said minimum value being of a second sufficient magnitude to permit current flow between the source and drain electrode of only the transistor at said one end of said row, whereby the number of field effect transistors in which electric current flows between the source and drain electrodes thereof varies linearly with respect to time.

Claim 3

A semiconductor scanning device for scanning digital signals in accordance with claim 1, wherein the gate insulator layers of individual field effect transistors are different from each other in thickness.

Claim 4

A semiconductor scanning device for scanning digital signals in accordance with claim 1, wherein the gate insulator layers of individual field effect transistors include different amounts of metallic ion with respect to each other.

Claim 5

A semiconductor scanning device comprising: a first and a second row of a plurality of metal-oxide semiconductor type field effect transistors, each transistor having a source, a gate and a drain region and a respective electrode connected thereto, disposed with substantially identical distances therebetween on one surface of a semiconductor substrate, said first and second rows having a same number N of transistors, the gate threshold voltage being lowest for the first and highest for the last of said field effect transistors of the rows and varying substantially linearly with distance from one end of each row to the other end thereof; first means for successively interconnecting the gate electrode of each field effect transistor to that of the gate electrode of a succeeding transistor; second means for connecting the source electrode of the nth field effect transistor of the first row of the drain electrode of the (N - n + 1)th field effect transistor of the second row, n being a positive integer not greater than N; third means, connected to the respective drain electrode of the nth field effect transistor of the first row and the source electrode of the (N - n + 1)th field effect transistor of the second row, for supplying an elecTric current thereto; fourth means, connected to the respective interconnected gate electrodes of the transistors of said first row,for applying electric pulses of a first saw-tooth waveform, the height of which increases linearly from a minimum to a maximum value with respect to time, said maximum value being of a first sufficient magnitude to permit electric current to flow between the drain and the source electrode of the Nth field effect transistor, said minimum value being of a second sufficient magnitude to permit electric current to flow between the drain and the source electrode of only the first field effect transistor of the first row, so that the number of field effect transistors in which electric current flows between the drain and the source electrode increases substantially linearly with time; and fifth means, connected to the respective interconnected gate electrodes of the transistors of said second row, for applying electric pulses of a second saw-tooth waveform, the height of which decreases linearly from a maximum to a minimum value with time, said maximum value being of a first sufficient level to permit electric current to flow between the drain and the source electrode of the Nth field effect transistor, said minimum value being of a second sufficient level to permit the electric current to flow between the drain and the source electrode of only the first field effect transistor of said second row, so that the number of field effect transistors in which electric current flows between the drain and the source electrode decreases substantially linearly with respect to time and so that a field effect transistor through which electric current flows shifts from one end to the other of the rows with a substantially constant velocity.

Claim 6

A semiconductor scanning device comprising: a first and a second row of a plurality of metal-oxide semiconductor type field effect transistors, each transistor having a source, a gate and a drain region and a respective electrode connected thereto, disposed with substantially identical distances therebetween on one surface of a semiconductor substrate, said first and second rows having a same number N of transistors, the gate threshold voltage being lowest for the first and highest for the last of said field effect transistors of the rows and varying substantially linearly with distance from one end of each row to the other end thereof; first means for successively interconnecting the gate electrode of each field effect transistor to that of the gate electrode of a succeeding transistor; second means for connecting the source electrode of the nth field effect transistor of the first row of the drain electrode of the (N - n + 1)th field effect transistor of the second row, n being a positive integer not greater than N; third means, connected to the respective drain electrode of the nth field effect transistor of the first row and the source electrode of the (N - n + 1)th field effect transistor of the second row, for supplying an elecTric current thereto; fourth means, connected to the respective interconnected gate electrodes of the transistors of said first row,for applying electric pulses of a first saw-tooth waveform, the height of which increases linearly from a minimum to a maximum value with respect to time, said maximum value being of a first sufficient magnitude to permit electric current to flow between the drain and the source electrode of the Nth field effect transistor, said minimum value being of a second sufficient magnitude to permit electric current to flow between the drain and the source electrode of only the first field effect transistor of the first row, so that the number of field effect transistors in which electric current flows between the drain and the source electrode increases substantially linearly with time; and fifth means, connected to the respective interconnected gate electrodes of the transistors of said second row, for applying electric pulses of a second saw-tooth waveform, the height of which decreases linearly from a maximum to a minimum value with time, said maximum value being of a first sufficient level to permit electric current to flow between the drain and the source electrode of the Nth field effect transistor, said minimum value being of a second sufficient level to permit the electric current to flow between the drain and the source electrode of only the first field effect transistor of said second row, so that the number of field effect transistors in which electric current flows between the drain and the source electrode decreases substantially linearly with respect to time and so that a field effect transistor through which electric current flows shifts from one end to the other of the rows with a substantially constant velocity.

Claim 7

A semiconductor scanning device for scanning digital signals in accordance with claim 4, wherein the gate insulator layers of individual field effect transistors are different from each other in the thickness.

Claim 8

A semiconductor scanning device for scanning digital signals in accordance with claim 4, wherein the gate insulator layers of individual field effect transistors include different amounts of metallic ion with respect to each other.

Claim 9

A semiconductor scanning device comprising: a plurality of voltage sensitive switching elements, arranged sequentially adjacent to one another, each having an input electrode, an output electrode and a control electrode, the application of a voltage to the control electrode of an element of a predetermined magnitude causing a conductive path to be provided between said input and output electrodes, whereby a signal supplied to said input electrode may be provided at the output electrode, and the voltage at which a conductive path is provided between an input electrode and an output electrode of the respective element being defined as the threshold voltage for said element, the threshold voltage of at least two of said elements in said plurality differing from each other; means for supplying a control voltage to the control electrodes of said plurality of comments simultaneously, the magnitude of which varies with time, whereby said at least two of said elements will be switched ON to provide a conductive path between their respective input and output electrodes at different instants of time, and wherein each of said voltage sensitive switching elements comprises a field effect transistor, the source and drain electrodes of which correspond to said input and output electrodes and the gate electrode of which corresponds to said control electrode, wherein said voltage sensitive switching elements are disposed in two parallel rows on a common substrate, into which the respective source and drain regions and the electrodes therefor of said field effect transistors are formed, and wherein the source and the drain of a respective field effect transistor adjacent another field effect transistor in separate rows are connected together, the common cOnnected gate electrodes being in the form of respective longitudinal conductive layers disposed on each gate insulator layer of respective field effect transistor in a parallel row, and wherein the thickness of said insulator layer is different for adjacent field effect transistors, to thereby provide different threshold voltages therefor.

Claim 10

A semiconductor scanning device comprising: a plurality of voltage sensitive switching elements, arranged sequentially adjacent to one another, each having an input electrode, an output electrode and a control electrode, the application of a voltage to the control electrode of an element of a predetermined magnitude causing a conductive path to be provided between said input and output electrodes, whereby a signal supplied to said input electrode may be provided at the output electrode, and the voltage at which a conductive path is provided between an input electrode and an output electrode of the respective element being defined as the threshold voltage for said element, the threshold voltage of at least two of said elements in said plurality differing from each other; means for supplying a control voltage to the control electrodes of said plurality of comments simultaneously, the magnitude of which varies with time, whereby said at least two of said elements will be switched ON to provide a conductive path between their respective input and output electrodes at different instants of time, and wherein each of said voltage sensitive switching elements comprises a field effect transistor, the source and drain electrodes of which correspond to said input and output electrodes and the gate electrode of which corresponds to said control electrode, wherein said voltage sensitive switching elements are disposed in two parallel rows on a common substrate, into which the respective source and drain regions and the electrodes therefor of said field effect transistors are formed, and wherein the source and the drain of a respective field effect transistor adjacent another field effect transistor in separate rows are connected together, the common cOnnected gate electrodes being in the form of respective longitudinal conductive layers disposed on each gate insulator layer of respective field effect transistor in a parallel row, and wherein the thickness of said insulator layer is different for adjacent field effect transistors, to thereby provide different threshold voltages therefor.

Claim 11

A semiconductor scanning device according to claim 7, wherein the thickness of the gate insulator layer for a respective row varies from one end of said longitudinal gate electrode to the other.

Claim 12

A semiconductor scanning device according to claim 7, wherein the ion dopant concentration of the gate insulator layer varies from one end of said longitudinal electrode to the other.

Claim 13

A semiconductor scanning device according to claim 7, including means for supplying first and second saw-tooth wave voltages to the longitudinal gate electrode layers of respective parallel rows of field effect transistors.

Claim 18

A semiconductor device comprising: a semiconductor substrate having a first conductivity type and having a main surface; a plurality of pairs of semiconductor regions of a second conductivity type opposite to said first conductivity type disposed in the main surface of said substrate, each pair of regions being spaced apart and each region of each pair being spaced with respect to each other; a first layer of insulator material disposed over each of said paiRs of regions and on said substrate, except for that portion of the substrate between the regions of said pairs of regions; a plurality of pairs of electrodes extending through said first layer of insulator material and contacting said respective pairs of regions; a second layer of insulator material disposed on said substrate overlying the portion thereof between the regions of said pairs of regions not covered by said first layer of insulator material, wherein the electronic characteristics of at least two portions of said second layer disposed between the regions of a pair are different for different pairs of regions; and an electrode layer disposed on said second layer of insulator material and extending continuously to overlie each portion of said substrate disposed between the regions of each pair of regions.

Claim 19

A semiconductor device comprising: a semiconductor substrate having a first conductivity type and having a main surface; a plurality of pairs of semiconductor regions of a second conductivity type opposite to said first conductivity type disposed in the main surface of said substrate, each pair of regions being spaced apart and each region of each pair being spaced with respect to each other; a first layer of insulator material disposed over each of said paiRs of regions and on said substrate, except for that portion of the substrate between the regions of said pairs of regions; a plurality of pairs of electrodes extending through said first layer of insulator material and contacting said respective pairs of regions; a second layer of insulator material disposed on said substrate overlying the portion thereof between the regions of said pairs of regions not covered by said first layer of insulator material, wherein the electronic characteristics of at least two portions of said second layer disposed between the regions of a pair are different for different pairs of regions; and an electrode layer disposed on said second layer of insulator material and extending continuously to overlie each portion of said substrate disposed between the regions of each pair of regions.

Claim 20

A semiconductor device according to claim 13, wherein the thickness of said second layer of insuating material is different for said at least two different portions.

Claim 21

A semiconductor device according to claim 14, wherein the thickness of said insulator material varies increasingly in the direction along said electrode layer.

Claim 22

A semiconductor device according to claim 13, wherein said second insulator layer has the dopant concentration thereof varying continuously over the length thereof beneath said electrode layer.