Patent US3762966A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3762966A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabricating high emitter efficiency semiconductor device with low base resistance by selective diffusion of base impurities

Assignee: General Electric Co
•
Filing: 1970-02-13
•
Granted: 1973-10-02
•
Expires: 1990-02-13
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A transistor, such as NPN type, for example, is fabricated by first diffusing a heavily doped P-type base contact region into an N-type semiconductor layer epitaxially grown on a heavily doped N-type semiconductor wafer. Holes are etched through the base contact region into the N-type layer and strongly N-type semiconductor material containing both N-type impurities and faster diffusing P-type impurities is epitaxially grown so as to fill the holes. The wafer is then heated to diffuse the P-type impurities so as to form a base region of controlled thickness, simultaneously forming emitter-base and base-collector junctions. Emitter contact is made by contacting the material epitaxially grown in the holes. Other type semiconductor devices, such as semiconductor controlled rectifiers, may also be fabricated in this manner.

Inventors

  • 👤 W Engeler
  • 👤 M Garfinkel

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 06:16
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D99/00; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/05; Y10S148/151

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 50 words
The method of claim 1 wherein said semiconductor material comprises silicon, said impurities of the one conductivity determining type comprise one of the group consisting of gallium, aluminum and boron, and said impurities of the opposite conductivity determining type comprise one of the group consisting of antimony, phosphorous and arsenic.
Claim 2
Dependent Claim 34 words
The method of claim 1 wherein said step of forming a base contact region comprises diffusing impurities of the one conductivity determining type in a specific concentration into said material of opposite type conductivity.
Claim 3
Dependent Claim 33 words
The method of claim 1 wherein said step of forming a contact region comprises epitaxially depositing said one type conductivity semiconductor material atop said major surface of said opposite type conductivity semiconductor material.
Claim 4
Dependent Claim 59 words
The method of claim 1 wherein the step of etching at least one hole through said contact region comprises the steps of covering the surface of said contact region with an insulating coating, forming at least one opening in said insulating coating, and etching each said hole in the area exposed by each said opening in said insulating coating.
Claim 5
Dependent Claim 25 words
The method of claim 5 wherein said step of covering the surface of said contact region comprises thermally oxidizing the surface of said contact region.
Claim 6
Dependent Claim 70 words
The method of claim 5 including the additional steps of exposing a portion of the surface of said contact region, forming a first metallic coating in electrical contact with the exposed portion of the surface of said contact region, and forming a second metallic coating in electrical contact with said semiconductor material epitaxially grown through each said hole, said first and second metallic coatings being electrically isolated from each other.
Claim 7
Dependent Claim 43 words
The method of claim 1 wherein said semi-conductor material comprises silicon, said impurities of the one conductivity determining type comprise phosphorous, antimony, and arsenic, and said impurities of the opposite conductivity determining type comprise one of the group consisting of gallium and boron.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-10-01 1977-04-02 1977-10-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-10-01 1981-04-02 1981-10-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-10-01 1985-04-02 1985-10-02 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag