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US3761915A Expired / Lapsed US ⏱️ 0.0 years remaining

Output command decoder for numerical control equipment

Assignee: Bendix Corp
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Filing: 1972-04-26
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Granted: 1973-09-25
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Expires: 1992-04-26
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Abstract

Abstract The invention is directed to a system for decoding output commands from a computer utilized with a numerical control system. When a command is to be directed to a particular external device controlled by the N/C system, an eight bit word is addressed to a decoding system. The decoding system then decodes the eight bit word to actuate the particular device to be controlled. Hence, only one address need be utilized to control 256 external devices. The address is that of the decoding system. The invention thus preserves substantial address capacity in the computer of the N/C system and thereby greatly increases the flexibility of the system.

Inventors

  • 👤 H Henegar
  • 👤 R Patterson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 20:22
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/418; G05B19/4181; Y; Y02; Y02P; Y02P90/00; Y02P90/02

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 160 words
In a numerical control system, a command decoder for selectively controlling a plurality of devices by use of a command word decoded by said command decoder to selectively control said devices through said command decoder, in response to the actuation of said command decoder by the simultaneous reception of a decoder address signal and a device output signal, said command decoder comprising: first means for receiving said decoder address signal and said device output signal indicating that at least one of said devices is to be controlled, said means for receiving producing an actuating signal in response to the simultaneous reception of said decoder address signal and said device output signal; second means for receiving said actuating signal and said command word and producing a plurality of logic signals; third means for receiving said logic signals in parallel form and decoding said command word to produce decoded control signals for selectively controlling said devices in response to said command word.
Claim 2
Dependent Claim 160 words
In a numerical control system, a command decoder for selectively controlling a plurality of devices by use of a command word decoded by said command decoder to selectively control said devices through said command decoder, in response to the actuation of said command decoder by the simultaneous reception of a decoder address signal and a device output signal, said command decoder comprising: first means for receiving said decoder address signal and said device output signal indicating that at least one of said devices is to be controlled, said means for receiving producing an actuating signal in response to the simultaneous reception of said decoder address signal and said device output signal; second means for receiving said actuating signal and said command word and producing a plurality of logic signals; third means for receiving said logic signals in parallel form and decoding said command word to produce decoded control signals for selectively controlling said devices in response to said command word.
Claim 3
Dependent Claim 32 words
The command decoder of claim 1 wherein said third means for receiving includes a plurality of BCD-decade decoders so that said decoded control signals are available as pulse outputs of said decoders.
Claim 4
Dependent Claim 59 words
The command decoder of claim 1 wherein said command word includes a total of n logic ONE''s and ZERO''s; said second means for receiving is circuit means including n logic means for individually receiving said logic ONE''s and ZERO''s and producing logic ONE''s for each simultaneous occurrence of said actuating signal and said logic ONE''s of said command word.
Claim 5
Dependent Claim 50 words
The command decoder of claim 3 wherein said third means for receiving includes decoder means for receiving said logic ONE''s and ZERO''s from said logic means and decoding said logic ONE''s and ZERO''s to produce one of 2n possible combinations of decoded signals for energizing one of 2n possible devices.
Claim 6
Dependent Claim 97 words
In a numerical control system operative with a computer for sending command signals to devices controlled by said numerical control system, and wherein said computer provides ready signals for indicating that a command signal is available for application to one of said devices, an improvement comprising: a command decoder for receiving said ready signals and decoding and transferring said command signals to said devices in response to said ready signals, said commander decoder being addressed by said computer for all of said command signals so that all of said devices Can be controlled by a single address.
Claim 7
Dependent Claim 97 words
In a numerical control system operative with a computer for sending command signals to devices controlled by said numerical control system, and wherein said computer provides ready signals for indicating that a command signal is available for application to one of said devices, an improvement comprising: a command decoder for receiving said ready signals and decoding and transferring said command signals to said devices in response to said ready signals, said commander decoder being addressed by said computer for all of said command signals so that all of said devices Can be controlled by a single address.
Claim 8
Dependent Claim 37 words
The improvement of claim 5 wherein n logic pulses form said command signals and said command decoder includes n logic means individually receiving said logic pulses so that 2n devices can be energized by said command signals.
Claim 9
Dependent Claim 98 words
The improvement of claim 6 wherein said logic means each yield a logic ONE when simultaneously energized by said ready signal and a logic ONE pulse from said command signals, and said logic means each yield a logic ZERO when a command signal logic ZERO is received so that encoded logic ONE''s and ZERO''s, in parallel form, are supplied by said logic means; and further including subdecoder means receiving said encoded logic ONE''s and ZERO''s and producing 2n combinations of ONE''s and ZERO''s so that 2n devices can be individually energized by said computer through said command decoder.
Claim 10
Dependent Claim 31 words
The improvement of claim 7 wherein said subdecoder means includes a plurality of BCD-decade decoders, each of said decade decoders receiving four of said encoded logic pulses and producing decade outputs.
Claim 11
Independent Claim 111 words
A method of energizing 2n external devices using a single address stored within the computer of a numerical control system including the steps of: simultaneously providing a decoder address signal and a device output signal to produce an actuating signal; providing a command word composed of n arrangements of two logic states so that said 2n devices can be individually energized; combining said actuating signal and said command word and decoding the resulting combination to produce 2n combinations of decoded logic ONE''s and ZERO''s so that said 2n devices can be separately energized by said command word in accordance with the arrangement of logic ONE''s and ZERO''s in said command word.
Claim 12
Independent Claim 111 words
A method of energizing 2n external devices using a single address stored within the computer of a numerical control system including the steps of: simultaneously providing a decoder address signal and a device output signal to produce an actuating signal; providing a command word composed of n arrangements of two logic states so that said 2n devices can be individually energized; combining said actuating signal and said command word and decoding the resulting combination to produce 2n combinations of decoded logic ONE''s and ZERO''s so that said 2n devices can be separately energized by said command word in accordance with the arrangement of logic ONE''s and ZERO''s in said command word.
Claim 13
Dependent Claim 15 words
The method of claim 9 wherein said decoding is effected in a binary-coded decimal-decade fashion.

References Cited (Backward Citations)

US3239832A Cited
US3506815A Cited
US3535497A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-09-24 1977-03-26 1977-09-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-09-24 1981-03-26 1981-09-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-09-24 1985-03-26 1985-09-25 $7700.00 Window Closed / Lapsed

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