Combined digital multiplication summation

Claim 1

An arithmetic unit for combined digital multiplication and summation of the form A+C.D using independent operands A, C and D without discrete intermediate storage of any sum of any partial product comprising: a. means for generating electrical signals representative of digital functions A, C and D, b. a multiplier recoding unit to recode said electrical signal representative of C, c. a summands unit to combine said electrical signal representative of D and the output of said multiplier recoding unit into a set of partial products, d. a family of pseudoadders for summing the partial products from said summands unit, each of said pseudoadders including a plurality of adder circuits, each adder circuit adapted for adding bits of data to produce a sum and carry output bit, said adder circuits having, 1. a first, second and third input, 2. a first nand circuit having said first, second and third inputs applied thereto, 3. a fifth circuit having said first and third inputs applied thereto, 4. an exclusive nor circuit having said first, second and third inputs applied thereto, 5. a second nand circuit having said second input and the output from said exclusive nor circuit applied thereto, 6. a fourth nand circuit having said first input, the output from said fifth nand circuit and the output from said exclusive nor circuit applied thereto, 7. a third nand circuit having said third input, the output from said fifth nand circuit, and the output from said exclusive nor circuit applied thereto, 8. a sixth nand circuit having the outputs from said first, second, third and fourth nand circuits applied thereto to produce a sum output from said adder circuit, and 9. a seventh nand circuit having the outputs of said fifth nand circuit and said exclusive nor circuit applied thereto to produce a carry output from said adder circuit, e. exclusively combinational logic means responsive to and initiated by said electrical signals representative of digital functions C and D including said family of pseudoadders for maintaining a continuous flow of digital electrical signals in converging combinational logic paths of said pseudoadders for production of an ultimate sum with the production at each of a plurality of pseudoadder levels of electrical signals representative of the sums of the partial products of the digital representations of C and D wherein said sums of partial products progressively decrease in number along said path to produce an ultimate sum representative of C.D in the forM of a sum and carry pair, and f. combinational logic means for introducing into said flow of electrical signals following formation of said ultimate sum said function representative of A to form an output signal representative of the sum of A and said ultimate sum.

Claim 41

A system of performing the operation A+C.D, which comprises: a. means for generating electrical signals representative of digital physical functions, A, C, and D, b. combinational logic means for gEnerating digitally all of the partial products of said functions C and D, c. pseudoadder tree means for generating digital sums of said partial products at each of a plurality of pseduoadder levels with means for simultaneously generating all sums at any level in said pseudoadders, each pseudoadder of said tree including a plurality of adders, each of said adders having

Claim 42

A system of performing the operation A+C.D, which comprises: a. means for generating electrical signals representative of digital physical functions, A, C, and D, b. combinational logic means for gEnerating digitally all of the partial products of said functions C and D, c. pseudoadder tree means for generating digital sums of said partial products at each of a plurality of pseduoadder levels with means for simultaneously generating all sums at any level in said pseudoadders, each pseudoadder of said tree including a plurality of adders, each of said adders having