Rate adaptive nonsynchronous demodulator apparatus

Claim 2

A nonsynchronous demodulator apparatus in which the improvement comprises: input means for supplying to the input of the demodulator a series binary input signal of two level nonsynchronous binary bits having a nonuniform bit rate; dynamic time reference means for determining the width of successive ones of said input bits, and for producing a dynamic time reference signal corresponding to the width of each input bit so that the value of said reference signal is automatically changed in response to changes in the width of said input bits due to variations in the bit rate; and comparator means for comparing the input bits with the reference signal corresponding to the next preceding input bit to determine whether the compared input bit is a binary one bit or a zero bit for producing a series binary output signal or output pulses corresponding to said input signal but of a different code; said comparator means also compAring said reference signal with space width signals corresponding to the widths of the spaces between successive input bits and producing a stop pulse when a space width signal exceeds said reference signal thereby indicating the end of the input signal.

Claim 3

A demodulator apparatus in accordance with claim 1 in which the binary input bits are pulses of two different widths.

Claim 4

A demodulator apparatus in accordance with claim 1 which also includes a compensation means separate from said reference means to enable the reference signal produced by one bit type of binary input pulse to be compared with another bit type of input pulse as well as with said one type of binary input pulse.

Claim 5

A demodulator apparatus in accordance with claim 3 in which the comparator means includes a comparator counter for counting digital pulses having its input connected through the compensation means and a comparator gate means to the output of a clock pulse generator, said comparator gate means being rendered conducting by the input signal, and said compensation means changing the count rate of said comparator counter to compensate for the different width input pulses.

Claim 6

A demodulator in accordance with claim 4 in which the compensation means includes a memory means for storing the binary value according to the last bit output pulse and for operating the comparator gate means to increase the frequency of compensated clock pulses produced at the output of said compensation means which are applied to the comparator counter during an input pulse following a preceding input pulse of wide bit type and to decrease the frequency of said compensated clock pulses during an input pulse following a preceding input pulse of narrow bit type.

Claim 7

A demodulator apparatus in accordance with claim 1 in which the input bits include binary information bits arranged in groups, and preamble bits positioned at the beginning of each group.

Claim 8

A demodulator apparatus in accordance with claim 1 in which the timing reference means includes a first digital counter, a clock pulse generator and first gate means for applying clock pulses of predetermined frequency from said clock generator to the input of said first counter when said gate means is gated on by said input bits.

Claim 9

A demodulator apparatus in accordance with claim 7 which includes a transfer means for transferring the complement of the first counter output voltage in parallel from said first counter to a second counter in said comparator means to provide said reference signal for comparison with said input bits by said second counter.

Claim 10

A demodulator apparatus in accordance with claim 8 in which the second counter also operates as a space width comparator means for comparing said reference signal with a space width signal corresponding to the space between successive input pulses, and produces a stop pulse when said space width signal exceeds said reference signal indicating the end of said input signal.

Claim 11

A demodulator apparatus in accordance with claim 9 in which the space width comparator means also includes and a third gate means connected between the input of said second counter and the output of said compensation means, said third gate means being gated on to transmit compensated clock pulses only during the space between said input pulses.

Claim 12

A demodulator apparatus in accordance with claim 1 which also includes means for producing shift output pulses that are synchronized with the information bits of the output signal.

Claim 13

A nonsynchronous demodulator apparatus in which the improvement comprises: input means for supplying to the input of the demodulator a nonsynchronous binary input signal of two levels that is comprised of a series of binary pulses having the same amplitude and polarity but two different widths corresponding to different bits with the width of the wider pulse being at least twice the width of the narrower pulse; timing means for determining the widths of successive ones of said input pUlses and for producing width signals corresponding to said pulse widths; a first dynamic time reference means for producing a first time reference signal whose duration is proportional to said width signal obtained from the previous input pulse by a first predetermined proportionality factor and which begins coincident with the start of the succeeding input pulse; a first comparator means for comparing the duration of said first time reference signal with the width of the next succeeding input pulse in order to classify said input pulse as to whether it is of the wide or the narrow type and for producing a series binary output signal in which demodulated binary data are represented by two different voltage states at the output; a second dynamic time reference means for producing a second time reference signal whose duration is proportional to said width signal obtained from the previous input pulse by a second predetermined proportionality factor and which begins coincident with the start of the succeeding input space; a second comparator means for comparing the duration of said second time reference signal with the duration of the space between said input pulses for determining when input pulses have ceased and then generating an output stop pulse, and for terminating said timing means and said first and second reference means in preparation for receiving the next series of input pulses; and a compensating means for causing said first and second time reference signals to have durations which are proportional to said width signals but are independent of which of the two types of input pulses produced said width signal.

Claim 14

A nonsynchronous demodulator apparatus in which the improvement comprises: input means for supplying to the input of the demodulator a nonsynchronous binary input signal of two levels that is comprised of a series of binary pulses having the same amplitude and polarity but two different widths corresponding to different bits with the width of the wider pulse being at least twice the width of the narrower pulse; timing means for determining the widths of successive ones of said input pUlses and for producing width signals corresponding to said pulse widths; a first dynamic time reference means for producing a first time reference signal whose duration is proportional to said width signal obtained from the previous input pulse by a first predetermined proportionality factor and which begins coincident with the start of the succeeding input pulse; a first comparator means for comparing the duration of said first time reference signal with the width of the next succeeding input pulse in order to classify said input pulse as to whether it is of the wide or the narrow type and for producing a series binary output signal in which demodulated binary data are represented by two different voltage states at the output; a second dynamic time reference means for producing a second time reference signal whose duration is proportional to said width signal obtained from the previous input pulse by a second predetermined proportionality factor and which begins coincident with the start of the succeeding input space; a second comparator means for comparing the duration of said second time reference signal with the duration of the space between said input pulses for determining when input pulses have ceased and then generating an output stop pulse, and for terminating said timing means and said first and second reference means in preparation for receiving the next series of input pulses; and a compensating means for causing said first and second time reference signals to have durations which are proportional to said width signals but are independent of which of the two types of input pulses produced said width signal.

Claim 15

A demodulating apparatus in accordance with claim 12 in which the timing means includes a first digital counter, a reset means to start said first counter counting up from zero, a clock pulse generator and a first gate means for applying clock pulses of a predetermined frequency from said clock generator to the input of said first counter when said first gate means is gated on during said input pulses so that at the end of said input pulses said first counter contains a width signal which is a digital number whose magnitude is proportional to the width of said input pulses.

Claim 16

A demodulating apparatus in accordance with claim 13 in which the first reference means includes a second digital counter, a transfer means by which the complement of said first value present in said first counter is preset into said second digital counter at the end of said input pulse, a second gate means for applying clock pulses from said clock generator to the input of said second counter when said second gate means is gated on during said input pulses, and a pulse suppression means for regularly eliminating a predetermined fraction of said clock pulses from the input of said second digital counter.

Claim 17

A demodulating apparatus in accordance with claim 14 in which the first comparator means includes a last bit memory means for storing the state of the last stage of said second digital counter at the instant that said input pulse end, said state being zero when said input pulse is of the narrow kind and said state being one when said input pulse is of the wider kind.

Claim 18

A demodulating apparatus in accordance with claim 15 in which the second reference means includes said second digital counter, a transfer means by which the complement of said width signal present in said first counter is preset into said third digital counter at the end of said input pulse, and a third gate means for applying clock pulses from said clock generator to the input of said second counter when said third gate means is gated on during the space between said input pulses.

Claim 19

A demodulating apparatus in accordance with claim 16 in which the compensating means includes a fourth gating means by which the second digital counter is caused to count when a wide type succeeding input pulse is compared with a first reference signal produced at double the rate by the width signAl of a narrow type preceeding input pulse.

Claim 20

A demodulating apparatus in accordance with claim 16 in which the second comparator means includes said second counter whose last stage reaches the one state when the duration of the space between said input pulses exceeds a predetermined number of integral widths of said compensated timing reference signals for generating a stop signal at the demodulator output to denote the end of a group of said input signals.