Patent US3760288A successfully refreshed from Google Patents.
US3760288A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Operational amplifier
Assignee: Motorola Solutions Inc
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Filing: 1971-08-09
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Granted: 1973-09-18
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Expires: 1991-08-09
Abstract
Abstract An operational amplifier having a broad bandwidth, very low power consumption and an externally variable bias current which adjusts the bias of various stages of the amplifier. The externally adjustable bias allows the adjustment of bias for various supply voltages and operating conditions and allows the operation of the amplifier on supply voltages as low as plus or minus one volt with a power dissipation as low as 60 microwatts. Active loads are used for each stage of the amplifier and the broadband capability of the amplifier is obtained by relatively low reflected resistances which determine the time constant of certain of the stages in the amplifier. In an integrated circuit configuration, improved stability and common mode rejection are achieved by forming a plurality of transistors in a common base pocket.
Inventors
- 👤 P Leonard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:12
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/189; H03F3/19; H03F3/195; H10; H10D; H10D99/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
425 words
A transistor amplifier having first and second input terminals, first and second power supply terminals, an output terminal, a bias terminal, first, second, thrid, fourth, fifth, sixth and seventh transistors of a first conductivity type, eighth, ninth, tenth, eleventh and twelfth transistors of a second conductivity type, each of said transistors of said first and second conductivity types having an emitter, a base and a collector; first and second diode means, and first, second, third and fourth resistors, wherein said first and second input terminals are coupled to said bases of said first and second transistors respectively, said emitter of said first and second transistors are coupled together and to said collector of said third transistor, said emitter of said third transistor is coupled to said first power supply terminal, said base of said third transistor is coupled to said bias terminal, to said base and said collector of said fourth transistor, and To said base of said fifth transistor, said emitters of said fourth and fifth transistors are coupled to said first power supply terminal, said collectors of said first and second transistors are coupled to said collectors of said eighth and ninth transistors respectively, said emitters of said eighth and ninth transistors are coupled to said second power supply terminal, said collector of said eighth transistor is coupled to said bases of said eighth, ninth and tenth transistors, said emitter of said tenth transistor is coupled to said second power supply terminal, said collector of said tenth transistor is coupled through said first and second diodes to said collector of said sixth transistor, said emitter of said sixth transistor is coupled through said first resistor to said first power supply terminal, said base of said sixth transistor is coupled to said collectors of said fifth and eleventh transistors, said base of said eleventh transistor is coupled to said collector of said second transistor, said emitter of said eleventh transistor is coupled to said second power supply terminal through said second resistor, said collector of said seventh transistor is coupled to said second power supply terminal, said base of said seventh transistor is coupled to said collector of said tenth transistor, said emitter of said seventh transistor is coupled through said third resistor to said output terminal, said output terminal also being coupled through said fourth resistor to said emitter of said twelfth transistor, said base of said twelfth transistor is coupled to said collector of said sixth transistor, and said collector of said twelfth transistor is coupled to said first power supply terminal.
Claim 2
Dependent Claim
425 words
A transistor amplifier having first and second input terminals, first and second power supply terminals, an output terminal, a bias terminal, first, second, thrid, fourth, fifth, sixth and seventh transistors of a first conductivity type, eighth, ninth, tenth, eleventh and twelfth transistors of a second conductivity type, each of said transistors of said first and second conductivity types having an emitter, a base and a collector; first and second diode means, and first, second, third and fourth resistors, wherein said first and second input terminals are coupled to said bases of said first and second transistors respectively, said emitter of said first and second transistors are coupled together and to said collector of said third transistor, said emitter of said third transistor is coupled to said first power supply terminal, said base of said third transistor is coupled to said bias terminal, to said base and said collector of said fourth transistor, and To said base of said fifth transistor, said emitters of said fourth and fifth transistors are coupled to said first power supply terminal, said collectors of said first and second transistors are coupled to said collectors of said eighth and ninth transistors respectively, said emitters of said eighth and ninth transistors are coupled to said second power supply terminal, said collector of said eighth transistor is coupled to said bases of said eighth, ninth and tenth transistors, said emitter of said tenth transistor is coupled to said second power supply terminal, said collector of said tenth transistor is coupled through said first and second diodes to said collector of said sixth transistor, said emitter of said sixth transistor is coupled through said first resistor to said first power supply terminal, said base of said sixth transistor is coupled to said collectors of said fifth and eleventh transistors, said base of said eleventh transistor is coupled to said collector of said second transistor, said emitter of said eleventh transistor is coupled to said second power supply terminal through said second resistor, said collector of said seventh transistor is coupled to said second power supply terminal, said base of said seventh transistor is coupled to said collector of said tenth transistor, said emitter of said seventh transistor is coupled through said third resistor to said output terminal, said output terminal also being coupled through said fourth resistor to said emitter of said twelfth transistor, said base of said twelfth transistor is coupled to said collector of said sixth transistor, and said collector of said twelfth transistor is coupled to said first power supply terminal.
Claim 3
Dependent Claim
19 words
The amplifier of claim 1 wherein said first and second resistors each have a resistance of approximately 5000 ohms.
Claim 4
Dependent Claim
19 words
The amplifier of claim 1 wherein said third and fourth resistors each have a resistance of approximately 250 ohms.
Claim 5
Dependent Claim
51 words
The amplifier of claim 1 further comprised of a thirteenth transistor of a first conductivity type, having an emitter, a base and a collector, wherein said emitter, said base and said collector of said thirteenth transistor is coupled to said emitter, said base and said collector of said third transistor, respectively.
Claim 6
Dependent Claim
43 words
The amplifier of claim 1 wherein said transistors of a first conductivity type are NPN transistors, said transistors of a second conductivity type are PNP transistors and said first and second power supply tenminals are the negative and positive power supply terminals, respectively.
Claim 7
Dependent Claim
46 words
The amplifier of claim 5 wherein said amplifier is an integrated circuit amplifier formed in an N conductivity type silicon chip and said bases of said eighth, ninth and tenth PNP transistors have a common base region formed by a portion of said N type chip.
Claim 8
Dependent Claim
287 words
A differential input amplifier comprising first and second transistors of a first conductivity type, third, fourth and fifth transistors of a second conductivity type, a bias current determining means, an output amplifier and a coupling means, each of said transistors having an emitter, a base and a collector, the bases of said first and second transistors each being coupled to one of two differential input connections, the emitters of said first and second transistors being coupled together and through said bias current determining means to a first power supply terminal, said collector of said first transistor being coupled to said collector and said base of said third transistor, and to said base of said fourth transistor, said collector of said second transistor being coupled to said collector of said fourth transistOr and to an output connection of said differential input stage, said emitters of said third and fourth transistors being coupled to a second power supply terminal, said output amplifier having an input connection, a bias current connection and an output terminal and being a means for presenting an output signal at said output terminal responsive to the currents applied to said input connection and said bias current connection, said fifth transistor having its collector coupled to said bias current connection, its emitter coupled to said second power supply terminal and its base coupled to said bases of said third and fourth transistors; said coupling means being cOupled between said collector of said second transistor and said input connection of said output amplifier and being a means for coupling a signal to said input connection which is responsive to the difference in current in said collector of said fourth transistor and said collector of said second transistor.
Claim 9
Dependent Claim
287 words
A differential input amplifier comprising first and second transistors of a first conductivity type, third, fourth and fifth transistors of a second conductivity type, a bias current determining means, an output amplifier and a coupling means, each of said transistors having an emitter, a base and a collector, the bases of said first and second transistors each being coupled to one of two differential input connections, the emitters of said first and second transistors being coupled together and through said bias current determining means to a first power supply terminal, said collector of said first transistor being coupled to said collector and said base of said third transistor, and to said base of said fourth transistor, said collector of said second transistor being coupled to said collector of said fourth transistOr and to an output connection of said differential input stage, said emitters of said third and fourth transistors being coupled to a second power supply terminal, said output amplifier having an input connection, a bias current connection and an output terminal and being a means for presenting an output signal at said output terminal responsive to the currents applied to said input connection and said bias current connection, said fifth transistor having its collector coupled to said bias current connection, its emitter coupled to said second power supply terminal and its base coupled to said bases of said third and fourth transistors; said coupling means being cOupled between said collector of said second transistor and said input connection of said output amplifier and being a means for coupling a signal to said input connection which is responsive to the difference in current in said collector of said fourth transistor and said collector of said second transistor.
Claim 10
Dependent Claim
140 words
The operational amplifier of claim 7 further comprised of a sixth transistor of a first conductivity type and a bias current determining means, and wherein said coupling means is comprised of seventh transistor of a second conductivity type and a resistor, each of said transistors having an emitter, a base and a collector, said seventh transistor having its emitter coupled to said second power supply terminal through said resistor, its said base coupled to said collector of said second transistor and its said collector coupled to said collector of said sixth transistor and to said input connection of said output stage, said sixth transistor having its emitter coupled to said first power supply terminal and its base coupled to said bias current determining means, said bias current determining means being a means for controlling the current in said sixth transistor.
Claim 11
Dependent Claim
64 words
The operational amplifier of claim 8 wherein said bias current determining means is comprised of an eighth transistor of a first conductivity type having an emitter, a base and a collector, said eighth transistor having its emitter coupled to said first power supply terminal and its base and collector coupled to a bias current input terminal and to said base of said sixth transistor.
Claim 12
Dependent Claim
44 words
The operational amplifier of claim 9 wherein said transistors of a first conductivity type are NPN transistors, said transistors of a second conductivity type are PNP transistors and said first and second power supply terminals are the negative and positive power supply terminals respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-17 | 1977-03-19 | 1977-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-17 | 1981-03-19 | 1981-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-17 | 1985-03-19 | 1985-09-18 | $7700.00 | Window Closed / Lapsed |