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US3760105A Expired / Lapsed US ⏱️ 0.0 years remaining

Traffic monitor for data processing system

Assignee: AG Communication Systems Corp
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Filing: 1972-05-01
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Granted: 1973-09-18
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Expires: 1992-05-01
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Abstract

Abstract In the register-sender subsystem of a telephone switching system, the traffic monitor for determining the number of busy registers in order to distinguish periods of heavy traffic from light traffic comprises a counter, and comparison circuits, with a set of thumbwheel switches in a control center for setting a predetermined number, the comparison circuits being arranged to indicate when the number of busy registers is equal to or exceeds the setting on the thumbwheel switches. The register-sender is of the time-division multiplex type having common logic circuits and a memory which stores information relating to a state of a call, including processing sequence state information which indicates various states including an idle state. The registers have access to the memory and common logic circuits during sequential time slots, and during each time slot when the information for a register is read from memory, the processing sequence state indication is supplied to the counter so as to advance the counter if the register is busy. The settings on the thumbwheel switches include a cut-in level and a cut-out level, and separate comparison circuits are used for comparing the settings against the same counter. There are separate counters and comparison circuits as well as sets of thumbwheel switches for incoming registers and local registers.

Inventors

  • 👤 S Puccini

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 21:30
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54575; H04Q3/54591

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 366 words
In a data processing system having a plurality of peripheral units for connection to lines to receive data signals; processing and storage apparatus comprising a memory and logic circuits shared on a time division multiplex basis, said memory having sets of storage elements, a plurality of registers individually associated with said peripheral units each register comprising a block with a given number of said sets including at least one process control set which includes a process-sequence-state store for storing sequence state information, a source of cyclically recurring pulses supplied to the memory, a multiplex arrangement associating each register with an individual pulse time slot during which the information in the corresponding memory block is read via read circuits into a read buffer, selectively modified by means of the logic circuts, and written back into the block via write circuits, so that during a portion of the time slot for a register the information including that from its process control set, appears in the read buffer, data signal information being received by logic circuits from the peripheral units during the associated time slots for storage in the memory; a traffic monitor comprising counting means, a settable device in which a predetermined number is set, and comparison means having inputs connected to the counting means and to the settable device to compare the signals therefrom representing the numbers stored therein to produce an output when the numbers are equal; means coupling the input of the counting means to outputs of the read buffer corresponding to said process-sequence-state store to advance the counting means during each time slot in response to a given status condition indication, a bistable device connected to the output of said comparison means to be set in response to the output signal therefrom so that the set state of the bistable device indicates that the counting means have been advanced to a number equal to or exceeding said predetermined number, and means to reset the counting means and the bistable device once each cycle; whereby the set state of the bistable device indicates that the number of registers and associated peripheral units having the given status condition each cycle equals or exceeds the predetermined number.
Claim 2
Dependent Claim 366 words
In a data processing system having a plurality of peripheral units for connection to lines to receive data signals; processing and storage apparatus comprising a memory and logic circuits shared on a time division multiplex basis, said memory having sets of storage elements, a plurality of registers individually associated with said peripheral units each register comprising a block with a given number of said sets including at least one process control set which includes a process-sequence-state store for storing sequence state information, a source of cyclically recurring pulses supplied to the memory, a multiplex arrangement associating each register with an individual pulse time slot during which the information in the corresponding memory block is read via read circuits into a read buffer, selectively modified by means of the logic circuts, and written back into the block via write circuits, so that during a portion of the time slot for a register the information including that from its process control set, appears in the read buffer, data signal information being received by logic circuits from the peripheral units during the associated time slots for storage in the memory; a traffic monitor comprising counting means, a settable device in which a predetermined number is set, and comparison means having inputs connected to the counting means and to the settable device to compare the signals therefrom representing the numbers stored therein to produce an output when the numbers are equal; means coupling the input of the counting means to outputs of the read buffer corresponding to said process-sequence-state store to advance the counting means during each time slot in response to a given status condition indication, a bistable device connected to the output of said comparison means to be set in response to the output signal therefrom so that the set state of the bistable device indicates that the counting means have been advanced to a number equal to or exceeding said predetermined number, and means to reset the counting means and the bistable device once each cycle; whereby the set state of the bistable device indicates that the number of registers and associated peripheral units having the given status condition each cycle equals or exceeds the predetermined number.
Claim 3
Dependent Claim 39 words
In a data processing system, the combination as claimed in claim 1, wherein said settable device comprises manual switch means for setting the predetermined number; and wherein said given status indication is the busy condition of a peripheral unit.
Claim 4
Dependent Claim 249 words
In a data processing system, the combination as claimed in claim 2, wherein there are two of said settable devices comprising manual switch means for setting separate predetermined numbers for cut-in level and cut-out level respectively, and wherein there are two of said comparison means for cut-in level and cut-out level respectively, the comparison means for cut-in level having inputs from the settable device for the cut-in level and from the counting means, and the comparison means for cut-out level having inputs from the settable device for the cut-out level and the same counting means, and wherein there are two of said bistable devices connected respectively to indicate the outputs of the two comparison means, wherein with the predetermined number for the cut-in level greater than the predetermined number for the cut-out level, if the number of peripheral units busy during a cycle is equal to or greater than the predetermined number for the cut-in level then both of the bistable devices are set, if the number of peripheral units busy during the cycle is less than the predetermined number for the cut-out level neither bistable device is set, and if the number of busy peripheral units is equal to or greater than the predetermined number for the cut-out level and less than the predetermined number for the cut-in level then the bistable device indicating the cut-out level only is set during the cycle, both of the bistable devices being reset once each cycle along with the counting means.
Claim 5
Dependent Claim 152 words
In a data processing system, the combination as claimed in claim 3, further including a common bistable device, gate means coupling the outputs of the cut-in level and cut-out level indicating bistable devices respectively to set and reset inputs of the common bistable device, means effective once each cycle before the reset of the cut-in level and cut-out level bistable devices and counting means, and effective after the counting of all of the busy peripheral units to enable said gating means to set the common bistable device in response to the cut-in level indicating bistable device being set, and to reset the common bistable device in response to the cut-out level indicating bistable device being in the reset condition, the common bistable device remaining in its previous state if the cut-in level indicating bistable device is in the reset condition and the cut-out level indicating bistable device is in the set condition.
Claim 6
Dependent Claim 184 words
In a data processing system, the combination as claimed in claim 4, wherein there are two categories of said peripheral units, with the register for each peripheral unit including a category-indication store (C1 of Row 1); wherein said traffic monitor, for each category of peripheral units, includes apparatus having its own said counting means, its own said comparison means, two of said settable devices, and cut-in level and cut-out level indicating bistable devices, and its own said common bistable device, whereby the common bistable device for each category may be controlled in accordance with its own cut-in level and cut-out level values; and wherein there is further a control bistable device (110), wherein the output of the read buffer corresponding to said category-indicating store controls the input to the counting means to advance the counting means in accordance with the status condition indication for the corresponding category of peripheral units, and wherein the category-indication from the read buffer also controls said control bistable device to be selectively set if the common bistable device for that category of peripheral units has been set each cycle.
Claim 7
Dependent Claim 37 words
In a data processing system which is part of a communication switching system, the combination as claimed in claim 5, wherein said pEripheral units are register junctors for connection to communication lines for receiving digital call information.
Claim 8
Dependent Claim 70 words
In a data processing system, the combination as claimed in claim 6, further including means responsive to the output of said control bistable device to provide a normal time-out of certain operations for conditions of light traffic as indicated by the control bistable device being in a reset condition, and to provide relatively fast time-out for said operations in response to the control bistable device being in a set condition.
Claim 9
Dependent Claim 86 words
In a data processing system, the combination as claimed in claim 7, further including manual switches for selecting the specific time-out values for conditions of heavy and light traffic for different ones of said selected operations, and wherein there is provided match comparison circuits for comparing the setting of the switches and the output of timing means, and wherein the setting of said control bistable device selects which outputs of the switches and timing means are compared, so that normal or fast time-out may be selected.

References Cited (Backward Citations)

US2909608A Cited
US3532827A Cited
US3601546A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-09-17 1977-03-19 1977-09-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-09-17 1981-03-19 1981-09-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-09-17 1985-03-19 1985-09-18 $7700.00 Window Closed / Lapsed

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