Patent US3758767A successfully refreshed from Google Patents.
US3758767A
Expired / Lapsed
US
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Digital serial arithmetic unit
Assignee: Individual
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Filing: 1971-10-19
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Granted: 1973-09-11
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Expires: 1991-10-19
Abstract
Abstract Digital serial arithmetic unit comprising: a unit for multiplying one-digit figures, an adding unit, three rows of input gates and a row of output gates. The outputs of the input gate rows are connected with the respective inputs of the multiplying unit and with those of the adding unit. The outputs of the multiplying unit are connected with the respective inputs of the adding unit while the outputs of the adding unit are connected with the inputs of the output gate row.
Inventors
- 👤 L Kantorovich
- 👤 V Tolstiev
- 👤 Y Fet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:39
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/4915; G06F7/4917
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
616 words
An arithmetic unit comprising: a unit for multiplying onedigit numbers including respective input gates; an adding unit including respective input and output gates, a first row, a second row and a third row of arithmetic unit input gates; a row of output gates of the arithmetic unit and a timing means; said adding unit comprising first and second code converters, a Single-place low-order digit adder, a single-place high-order digit adder and a carry counter; said gates being divided into groups in accordance with a predetermined code system; said multiplying unit having first factor inputs, second factor inputs, low-order digit outputs of the product and high-order digit outputs of the products; said multiplying unit including input gates arranged in first, second and third groups; said adding unit input gates consisting of first, second third, fourth and fifth groups; said adding unit output gates consisting of one group; said timing means being operative for ensuring sequences of operations of said arithmetic unit input and output gates to perform arithmetic operations; the inputs of said first group of multiplying unit input gates being connected with the inputs of said first group of adding unit input gates and with the outputs of all groups in said first row of arithmetic unit input gates; the inputs of said second group of multiplying unit input gates being connected with the inputs of said second group of adding unit input gates and with the outputs of all groups in said second row of arithmetic unit input gates; the inputs of said third group of multiplying unit input gates being connected with the inputs of said third group of adding unit input gates and with the outputs of all groups in said third row of arithmetic unit input gates; said first factor inputs of the multiplying unit being connected with the outputs of said first group of multiplying unit input gates and with the outputs of said third input gate group of said multiplying unit; said second factor inputs of the multiplying unit being connected with the outputs of said second input gate group of said multiplying unit; said fourth group of adding unit input gates being connected with said product low-order digit outputs of said multiplying unit; said fifth group of adding unit input gates being connected with said product high-order digit outputs of said multiplying unit; the outputs of said first group of adding unit input gates being connected with respective inputs of said first code converter of adding unit; the outputs of said second group of adding unit input gates being connected with respective inputs of said second code converter of adding unit; the inputs of said single-place low-order digit adder of the adding unit being connected with respective outputs of third and fourth input gate groups in the adding unit and with respective outputs of said first and second code converters in the adding unit; the inputs of said single-place high-order digit adder of the adding unit being connected with respective outputs of said fifth input gate group in the adder unit; the carry output of said single-place low-order digit adder of the adding unit being connected with respective inputs of said single-place high-order digit adder of the adding unit; the carry output of said single-place high-order digit adder of the adding unit being connected with the input of said carry counter of the adding unit; the sum outputs of said single-place low-order digit adder of the adding unit being connected with respective inputs of said group of adding unit output gates; the outputs of said group of adding unit output gates being connected with respective inputs of all groups in said row of output gates of the arithmetic unit.
Claim 2
Dependent Claim
616 words
An arithmetic unit comprising: a unit for multiplying onedigit numbers including respective input gates; an adding unit including respective input and output gates, a first row, a second row and a third row of arithmetic unit input gates; a row of output gates of the arithmetic unit and a timing means; said adding unit comprising first and second code converters, a Single-place low-order digit adder, a single-place high-order digit adder and a carry counter; said gates being divided into groups in accordance with a predetermined code system; said multiplying unit having first factor inputs, second factor inputs, low-order digit outputs of the product and high-order digit outputs of the products; said multiplying unit including input gates arranged in first, second and third groups; said adding unit input gates consisting of first, second third, fourth and fifth groups; said adding unit output gates consisting of one group; said timing means being operative for ensuring sequences of operations of said arithmetic unit input and output gates to perform arithmetic operations; the inputs of said first group of multiplying unit input gates being connected with the inputs of said first group of adding unit input gates and with the outputs of all groups in said first row of arithmetic unit input gates; the inputs of said second group of multiplying unit input gates being connected with the inputs of said second group of adding unit input gates and with the outputs of all groups in said second row of arithmetic unit input gates; the inputs of said third group of multiplying unit input gates being connected with the inputs of said third group of adding unit input gates and with the outputs of all groups in said third row of arithmetic unit input gates; said first factor inputs of the multiplying unit being connected with the outputs of said first group of multiplying unit input gates and with the outputs of said third input gate group of said multiplying unit; said second factor inputs of the multiplying unit being connected with the outputs of said second input gate group of said multiplying unit; said fourth group of adding unit input gates being connected with said product low-order digit outputs of said multiplying unit; said fifth group of adding unit input gates being connected with said product high-order digit outputs of said multiplying unit; the outputs of said first group of adding unit input gates being connected with respective inputs of said first code converter of adding unit; the outputs of said second group of adding unit input gates being connected with respective inputs of said second code converter of adding unit; the inputs of said single-place low-order digit adder of the adding unit being connected with respective outputs of third and fourth input gate groups in the adding unit and with respective outputs of said first and second code converters in the adding unit; the inputs of said single-place high-order digit adder of the adding unit being connected with respective outputs of said fifth input gate group in the adder unit; the carry output of said single-place low-order digit adder of the adding unit being connected with respective inputs of said single-place high-order digit adder of the adding unit; the carry output of said single-place high-order digit adder of the adding unit being connected with the input of said carry counter of the adding unit; the sum outputs of said single-place low-order digit adder of the adding unit being connected with respective inputs of said group of adding unit output gates; the outputs of said group of adding unit output gates being connected with respective inputs of all groups in said row of output gates of the arithmetic unit.
Claim 3
Dependent Claim
242 words
An arithmetic unit, as claimed in claim 1, in which the timing means comprises three reversible binary counters and three decoders where all digit outputs of the first reversible counter, except the high-order bit output, are connected to respective inputs of the first decoder, whose outputs are connected in a digit-by-digit manner to the first control inputs of all input gates in the respective first row groups; the second control inputs of all first row gates are connected in parallel to the zero output of the first reversible counter high-orDer digit; all digit outputs of the second reversible counter, except the high-order bit output, are connected to respective inputs of the second decoder, whose outputs are connected in a digit-by-digit manner to the first control inputs of all input gates in the respective second row groups; the second control inputs of all second row gates are connected in parallel to the zero output of the second reversible counter high-order digit; all digit outputs of the third reversible counter, except the high-order bit output, are connected to respective inputs of the third decoder, whose outputs are connected in digit-by-digit manner to the first control inputs of all input gates in the respective third row groups and to the control inputs in respective output gate groups of the arithmetic unit, the second control inputs of all third row gates are connected in parallel to the zero output of the third reversible counter high-order digit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-10 | 1977-03-12 | 1977-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-10 | 1981-03-12 | 1981-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-10 | 1985-03-12 | 1985-09-11 | $7700.00 | Window Closed / Lapsed |