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US3757239A Expired / Lapsed US ⏱️ 0.0 years remaining

Direct current amplifier drift reduction method

Assignee: Avco Corp
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Filing: 1971-12-02
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Granted: 1973-09-04
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Expires: 1991-12-02
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Abstract

Abstract Herein disclosed is a method of selecting the resistive and temperature co-efficient parameters of emitter resistors in the differential input transistor pair of a direct current amplifier. The amplifier comprises said pair together with cascaded amplifying means and means for degeneratively applying feedback signals to said pair. The amplifier further comprises means for equating the collector currents of said pair and adjusting the output voltage to zero for a starting condition under which said resistive parameters are zero. The method comprises these steps, in sequence: Changing the resistive parameters from zero at the starting condition to a known value of X each, MEASURING THE POTENTIAL ACROSS EACH SAID RESISTIVE PARAMETER, CHANGING EACH RESISTIVE PARAMETER TO A VALUE OF X plus Delta X, noting the resultant change in said potential, thus determining the relationship between ohmage change and change in said potential, AGAIN REDUCING THE RESISTIVE PARAMETERS TO ZERO, AND SUBJECTING THE AMPLIFIER TO A KNOWN TEMPERATURE CHANGE, DETERMINING THE DRIFT CHARACTERISTIC OF THE AMPLIFIER REFERRED TO THE INPUT (I.E., THE RELATIONSHIP BETWEEN AMBIENT TEMPERATURE CHANGE AND CHANGE IN SAID POTENTIAL), AND UTILIZING THE ABOVE RELATIONSHIPS TO PREDETERMINE DESIRED RESISTIVE AND TEMPERATURE CO-EFFICIENT PARAMETERS WHICH SHOULD BE POSSESSED BY SAID EMITTER RESISTORS.

Inventors

  • 👤 M Langan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 17:43
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/306; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 296 words
A multistage differential amplifier having improved drift compensating means comprising: a pair of signal input terminals; a pair of signal output terminals; positive and negative current supply terminals adapted to be connected to an electrical energy source; an input differential amplifier stage comprising a pair of common emitter transistors, each transistor having having a base and an emitter and a collector, the bases being individually coupled to said input terminals, a potentiometer, having end terminals connected to said collectors and an adjustable terminal connected to said positive supply terminal, for providing collector loads for said transistors, a pair of emitter load networks for said transistors, said emitter networks being connected to said negative current supply terminal, gain determining resistor connected between junction points on said emitter load networks, one of said emitter load networks including, between its respective junction point and its respective emitter, a resistor having a temperaure coefficient proportioned to compensate for drift, and additional amplifier stage means intercoupled between said collectors and said output terminals, said additional amplifier stage means comprising a pair of common-collector transistors each having a base and an emitter and a collector, collector load resistors in series between the collectors of the common-collector transistors and the negative supply terminals, a parallel resistance-capacitance, filter network between both emitters of the common-collector, transistors and said positive current supply terminal, and series resistance-capacticance biasing networks between the bases and collectors of said common-collector transistors, said additional amplifier stage means further including a pair of field-effect transistors having their gates connected to the collector of the common-collector transistors and their sources connected across said balancing resistor to provide degenerative feedback current means and their sources connected directly to said output terminals and individual load resistors between said drains and said positive supply terminal.
Claim 2
Dependent Claim 296 words
A multistage differential amplifier having improved drift compensating means comprising: a pair of signal input terminals; a pair of signal output terminals; positive and negative current supply terminals adapted to be connected to an electrical energy source; an input differential amplifier stage comprising a pair of common emitter transistors, each transistor having having a base and an emitter and a collector, the bases being individually coupled to said input terminals, a potentiometer, having end terminals connected to said collectors and an adjustable terminal connected to said positive supply terminal, for providing collector loads for said transistors, a pair of emitter load networks for said transistors, said emitter networks being connected to said negative current supply terminal, gain determining resistor connected between junction points on said emitter load networks, one of said emitter load networks including, between its respective junction point and its respective emitter, a resistor having a temperaure coefficient proportioned to compensate for drift, and additional amplifier stage means intercoupled between said collectors and said output terminals, said additional amplifier stage means comprising a pair of common-collector transistors each having a base and an emitter and a collector, collector load resistors in series between the collectors of the common-collector transistors and the negative supply terminals, a parallel resistance-capacitance, filter network between both emitters of the common-collector, transistors and said positive current supply terminal, and series resistance-capacticance biasing networks between the bases and collectors of said common-collector transistors, said additional amplifier stage means further including a pair of field-effect transistors having their gates connected to the collector of the common-collector transistors and their sources connected across said balancing resistor to provide degenerative feedback current means and their sources connected directly to said output terminals and individual load resistors between said drains and said positive supply terminal.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-09-03 1977-03-05 1977-09-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-09-03 1981-03-05 1981-09-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-09-03 1985-03-05 1985-09-04 $7700.00 Window Closed / Lapsed

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