Asynchronous circuit and system

Claim 2

An asynchronous circuit comprising a storage section, an output gate section and a control section, said storage section having multistable gate means providing at least three stable states, at least two information states and a neutral state; said control section having a first stable state; a number of information output leads equal in number to the number of information states of said storage section; said gate section being disposed between said storage section and said output leads; said gate section being responsive to signals developed by said control section when in said first stable state to develop on said output leads, signals indicative of the state of said storage section; means for switching said control section to an unstable state; said gate section being responsive to signals developed by said control section when in said unstable state to cause said gate section to develop on said output leads signals indicative of the neutral state of said storage section; said storage section including means responsive to said unstable state of said control section to cause said storage section to assume its neutral state and means for causing said control section to assume a further stable state when said storage section assumes said neutral state.

Claim 3

An asynchronous circuit according to claim 1 wherein is provided a plurality of said asynchronous circuits, each of said storage sections having a number of input leads equal in number to said output leads, said input leads of one of said circuits being Connected on a one-for-one basis to the output leads of each of the other of said circuits, means connected to each of said other of said circuits to determine when information is to be transferred to said one of said circuits from any one of the other of said circuits, said last mentioned means being responsive to transfer of information to said one circuit to enable transfer of information from another of said other circuits to said one circuit in sequence.

Claim 4

An asynchronous system according to claim 1 wherein is provided a plurality of said asynchronous circuits, each of said storage sections having a number of input leads equal in number to said output leads, means connecting said output leads of one of said circuits to said input leads of the other of said circuits on a one-for-one basis, means for sensing receipt of information from said one circuit by any of said other of said circuits, said sensing means producing transfer signals to said connecting means sequentially and successively, said connecting means being responsive to receipt of a transfer signal from said sensing means and a signal indicative of the neutral state having been obtained in the storage section of that one of the other of said circuits which has been selected by said sensing means to next receive information from said one of said circuits, to transfer information to said that one of the other of said circuits.

Claim 5

An asynchronous system for transmitting information in a forward direction comprising first and second asynchronous circuits each including a control section, a storage section, an output section, and an equal plurality of input leads and output leads, each said storage section having a plurality of gate means interconnected to provide a number of stable states equal to one more than said input leads, said stable states consisting of a neutral state and a plurality of information states, each said gate section being disposed between said storage section and said output leads of its associated circuit, output leads of said first circuit being connected to input leads of said second circuit on a one-for-one basis; said control section of said first circuit developing a first stable state signal when said second circuit is in its neutral state, said gate section being responsive to said signal to develop on said output leads signals indicative of the state of said storage section, means responsive to transfer of an information state to said second circuit for switching said control section to an unstable state, said control section producing when in said unstable state a second signal, said gate section developing signals on said output leads indicative of the neutral state of said storage section in response to receipt of said second signal, said storage section having means responsive to said second signal to switch said storage section to its neutral state and said control section being responsive to said storage section achieving the neutral state to switch said control section to a stable state.

Claim 6

An asynchronous system for transmitting information in a forward direction comprising first and second asynchronous circuits each including a control section, a storage section, an output section, and an equal plurality of input leads and output leads, each said storage section having a plurality of gate means interconnected to provide a number of stable states equal to one more than said input leads, said stable states consisting of a neutral state and a plurality of information states, each said gate section being disposed between said storage section and said output leads of its associated circuit, output leads of said first circuit being connected to input leads of said second circuit on a one-for-one basis; said control section of said first circuit developing a first stable state signal when said second circuit is in its neutral state, said gate section being responsive to said signal to develop on said output leads signals indicative of the state of said storage section, means responsive to transfer of an information state to said second circuit for switching said control section to an unstable state, said control section producing when in said unstable state a second signal, said gate section developing signals on said output leads indicative of the neutral state of said storage section in response to receipt of said second signal, said storage section having means responsive to said second signal to switch said storage section to its neutral state and said control section being responsive to said storage section achieving the neutral state to switch said control section to a stable state.

Claim 7

An asynchronous system according to claim 4 wherein said storage sections comprise a plurality of NAND gates each having a number of input leads equal to one less than the number of NAND gates and each having one output lead; each NAND gate having its output lead connected to a different input lead of each of the other of said NAND gates, the output lead of a first NAND gate being connected to receive said second signal from said control section, and the output leads of the other of said NAND gates each being connected to receive input information.

Claim 8

An asynchronous system according to claim 5 wherein each of said control sections comprises three NAND gates, each having two input leads and an output lead, one of said NAND gates having its output lead connected to an input lead of each of the other two NAND gates, a second of said NAND gates having its output lead connected to an input lead of said one of said NAND gates, another input lead of each of said one NAND gate and of the third of said NAND gates being connected together, and means responsive to signals on at least the output lead of the third of said NAND gates for applying signals to the other input lead of the second of said NAND gates.

Claim 9

An asynchronous system according to claim 6 wherein said one NAND gate of said control section of said first circuit is connected to the output lead of said first NAND gate of said storage section of said second circuit and wherein said output lead of said third of said NAND gates of said control section of said first circuit is connected to the output lead of said first NAND gate of said storage section of said first circuit.

Claim 10

An asynchronous system according to claim 5 wherein said storage section comprises 3 NAND gates.

Claim 11

An asynchronous system according to claim 5 wherein said storage section comprises at least 4 NAND gates.

Claim 12

An asynchronous circuit according to claim 4 wherein is provided a plurality of said systems, means for generating a gate signal upon determining concurrent storage of information in said second circuits of each of said systems, and means for applying said gate signal to said control section of each of said second circuits to operate their associated gate sections to gate out information stored in said second circuits of said systems.

Claim 13

An asynchronous system according to claim 4 comprising means for extracting information in parallel concurrently from said asynchronous circuits, said means for extracting comprising means for sensing transfer of information between said asynchronous circuits, said means for sensing developing a gate signal upon occurrence of a predetermined event in transfer of information between said asynchronous circuits, output means connected to the output leads of each of said asynchronous circuits to sense the state of each said asynchronous circuit, and means responsive to said gate signal for causing said output means to transfer information to an external circuit in accordance with the state of each said asynchronous circuit.

Claim 14

An asynchronous system according to claim 4 wherein said storage section comprises a plurality of NAND gates equal in number to one more than the information states of said storage section, each said NAND gate having a plurality of input leads and one output lead with connections such that the output lead of each of said NAND gates is connected to a different input lead of all the other said NAND gates.

Claim 15

An asynchronous system according to claim 12 further comprising means for transmitting information in a reverse direction, said last mentioned means including a plurality of second control sections and second gate sections having output leads, said second gate sections connected in series to transmit information in a direction opposite to the direction information is transmitted by said first mentioned gate sections, said second control sections controlling transmission of information through said second gate means, means connecting said output leads of said second gate sections to said output leads of said plurality of NAND gates on a one-for-one basis, means for selectively and exclusively enabling said first mentioned gate sections and means for selectively and exclusively enabling said second gate sections.

Claim 16

An asynchronous system according to claim 4 wherein said control sections each includes means for establishing a first and a second stable state in said control section, said means for establishing being responsive to switching of its associated storage section from an information state to its neutral state and to said storage section of the succeeding circuit being in said neutral state for establishing therein said first stable state, said means for establishing being further responsive to switching of its associated storage section from an information state to said neutral state and to said storage section of the succeeding circuit being in an information state for eStablishing therein said second stable state, said gate section being connected to respond to said second stable state of its associated control section to establish on its output leads signals indicative of the neutral state of its associated storage section.

Claim 17

An asynchronous system according to claim 4 further comprising a circuit for applying information in parallel concurrently to said storage sections of said circuits of said system, said circuit for applying information in parallel comprising for each asynchronous circuit, input gate means responsive to an input signal representing an information state of an asynchronous circuit for generating a plurality of information signals equal in number to said input leads of each said asynchronous circuits, said input gate means for each said asynchronous circuit being responsive to a common gate signal to transfer said information signals to said input leads of its associated storage section.

Claim 18

The combination according to claim 4 further comprising means for clearing said asynchronous system which comprises means for causing said second circuit to appear to the first circuit to be in the neutral state regardless of the condition of storage of information therein.

Claim 19

A plurality of chains of asynchronous circuits in which transfers of information between corresponding asynchronous circuits in each of said chains are affected concurrently, each of said circuits comprising a storage section and a gate section, said storage sections each comprising a plurality of interconnected logic gates providing a number of stable information states and one stable neutral state, a plurality of information input leads equal to the number of information states of said storage section, each of said asynchronous circuits having output leads equal to said input leads and an output gate section for controlling transfer to said output leads of signals indicative of the state of said storage section, means connecting said output leads to storage sections so as to provide at least two parallel chains of cascaded asynchronous circuits each chain having at least a first and a second asynchronous circuit, a plurality of control circuits, there being one control circuit for the corresponding storage and gate sections in each of said parallel chains, said control section having a first stable state, a second stable state and an unstable state, sensing means responsive to an information state in all of said corresponding storage sections of said second circuits of said chains for generating a first signal for establishing said first stable state in said control circuit associated with said first circuits of said chain, said gate means of said first circuits being responsive to said first stable state of said control section of said first circuits to establish on its associated output leads signals indicative of said neutral state, said sensing means being responsive to the neutral state being attained by each of said storage sections of said second circuits of said chains to switch said control section of said first circuits to said second stable state, said gate section being responsive to the second stable state of its associated control circuit to establish on said output leads signals indicative of the states of said storage sections of said first circuits, whereby information may be transferred to said storage sections of said second circuits, said sensing means generating said first signal in response to receipt of information by all said storage means of said second circuits, said control circuit of said first circuits including means responsive to said first signal being reestablished to switch to said unstable state and subsequently switch to said first stable state, said gate section being closed by both said latter states and said storage sections being responsive to said unstable state to switch to said neutral state.

Claim 20

A plurality of chains of asynchronous circuits in which transfers of information between corresponding asynchronous circuits in each of said chains are affected concurrently, each of said circuits comprising a storage section and a gate section, said storage sections each comprising a plurality of interconnected logic gates providing a number of stable information states and one stable neutral state, a plurality of information input leads equal to the number of information states of said storage section, each of said asynchronous circuits having output leads equal to said input leads and an output gate section for controlling transfer to said output leads of signals indicative of the state of said storage section, means connecting said output leads to storage sections so as to provide at least two parallel chains of cascaded asynchronous circuits each chain having at least a first and a second asynchronous circuit, a plurality of control circuits, there being one control circuit for the corresponding storage and gate sections in each of said parallel chains, said control section having a first stable state, a second stable state and an unstable state, sensing means responsive to an information state in all of said corresponding storage sections of said second circuits of said chains for generating a first signal for establishing said first stable state in said control circuit associated with said first circuits of said chain, said gate means of said first circuits being responsive to said first stable state of said control section of said first circuits to establish on its associated output leads signals indicative of said neutral state, said sensing means being responsive to the neutral state being attained by each of said storage sections of said second circuits of said chains to switch said control section of said first circuits to said second stable state, said gate section being responsive to the second stable state of its associated control circuit to establish on said output leads signals indicative of the states of said storage sections of said first circuits, whereby information may be transferred to said storage sections of said second circuits, said sensing means generating said first signal in response to receipt of information by all said storage means of said second circuits, said control circuit of said first circuits including means responsive to said first signal being reestablished to switch to said unstable state and subsequently switch to said first stable state, said gate section being closed by both said latter states and said storage sections being responsive to said unstable state to switch to said neutral state.

Claim 21

An asynchronous circuit according to claim 17 wherein said storage means includes said sensing means and whErein said sensing means produces said first signal when all of said storage sections are storing information.

Claim 22

An asynchronous circuit according to claim 17 wherein said sensing means comprises first gate means for producing a first control signal when any of said storage sections of said second circuits are in the information state, a plurality of second gate means each connected with a storage section of a different one of said second circuits to produce a second gate signal when its associated storage section is in an information state, said sensing means further comprising logic means responsive to said first control signal and to all of said second gate means producing said second gate signals to switch said control section of said first circuits to said first stable state.

Claim 23

An asynchronous circuit comprising a storage section capable of assuming at least three stable states, at least two information states and a neutral state; an output section and a control section, said storage section connected to provide on a number of output leads signals indicative of said at least three stable states, said control section having a first stable state; a number of output terminals equal in number to the number of output leads of said storage section; said output section being disposed between said storage section and said output terminals; means for applying signals on said output leads to said output section, said output section being responsive to signals developed by said control section when in said first stable state to develop on said output terminals signals indicative of the signals applied thereto; means for switching said control section to an unstable state; said output section being responsive to signals developed by said control section when in said unstable state to develop on said output terminals signals indicative of the neutral state of said storage section; said storage section including means responsive to said unstable state of said control section to cause said storage section to assume its neutral state and means for causing said control section to assume a further stable state when said storage section assumes said neutral state.

Claim 24

An asynchronous circuit comprising a storage section capable of assuming at least three stable states, at least two information states and a neutral state; an output section and a control section, said storage section connected to provide on a number of output leads signals indicative of said at least three stable states, said control section having a first stable state; a number of output terminals equal in number to the number of output leads of said storage section; said output section being disposed between said storage section and said output terminals; means for applying signals on said output leads to said output section, said output section being responsive to signals developed by said control section when in said first stable state to develop on said output terminals signals indicative of the signals applied thereto; means for switching said control section to an unstable state; said output section being responsive to signals developed by said control section when in said unstable state to develop on said output terminals signals indicative of the neutral state of said storage section; said storage section including means responsive to said unstable state of said control section to cause said storage section to assume its neutral state and means for causing said control section to assume a further stable state when said storage section assumes said neutral state.

Claim 25

In combination, a source of information signals capable of assuming a variety of conditions, an information storage means and an information transfer means, said information storage means including means capable of assuming various information identifying conditions and at least one neutral non-information carrying condition, said source including means capable of assuming said conditions, said information transfer means including means for inducing in said storage means an information carrying condition as a function of an information carrying condition of said source, additional means producing internally generated signals indicative of various states of said transfer and storage means, said internally generated signals including a first signal generated when said storage means is in a neutral state, and a second signal generated upon response of said storage means to information transfer from said transfer means; and in response only to said internally generated signals, said means for inducing being responsive to only said first signal to apply information to said storage means, and said source including further means responsive only to said second signal to cause said source to assume a neutral condition and thereafter to permit said source to assume another information carrying condition.

Claim 26

In combination, a source of information signals capable of assuming a variety of conditions, an information storage means and an information transfer means, said information storage means including means capable of assuming various information identifying conditions and at least one neutral non-information carrying condition, said source including means capable of assuming said conditions, said information transfer means including means for inducing in said storage means an information carrying condition as a function of an information carrying condition of said source, additional means producing internally generated signals indicative of various states of said transfer and storage means, said internally generated signals including a first signal generated when said storage means is in a neutral state, and a second signal generated upon response of said storage means to information transfer from said transfer means; and in response only to said internally generated signals, said means for inducing being responsive to only said first signal to apply information to said storage means, and said source including further means responsive only to said second signal to cause said source to assume a neutral condition and thereafter to permit said source to assume another information carrying condition.

Claim 27

An asynchronous circuit comprising a storage section, an output gate section, a control section and an information output lead, said storage section including at least one storage flip-flop having an output lead, said flip-flop establishing either of two possible signals on said output lead depending upon the state of said flip-flop, an output gate of said output gate section disposed between said output lead of said flip-flop and said information output lead, said control section having means for establIshing first and second control signals, said output gates being responsive to a first of said control signals to open said gate and establish on said information output lead a signal indicative of the signal on said flip-flop output lead and means responsive to said second signal of said control section to close said output gate and reset said storage flip-flop to a predetermined condition to establish a specified one of said two possible signals on said flip-flop output lead.

Claim 28

An asynchronous circuit comprising a storage section, an output gate section, a control section and an information output lead, said storage section including at least one storage flip-flop having an output lead, said flip-flop establishing either of two possible signals on said output lead depending upon the state of said flip-flop, an output gate of said output gate section disposed between said output lead of said flip-flop and said information output lead, said control section having means for establIshing first and second control signals, said output gates being responsive to a first of said control signals to open said gate and establish on said information output lead a signal indicative of the signal on said flip-flop output lead and means responsive to said second signal of said control section to close said output gate and reset said storage flip-flop to a predetermined condition to establish a specified one of said two possible signals on said flip-flop output lead.

Claim 29

An asynchronous system for transmitting information comprising first and second asynchronous circuits each including a control section, a storage section comprising at least one flip-flop, an output gate section and an equal plurality of input and output leads, each said asynchronous circuit establishing signals indicative of information and neutral states, said output gate section being disposed between said storage section and said output leads of its associated asynchronous circuit, output leads of each said asynchronous circuit being connected to input leads of the other of said asynchronous circuit, on a one-for-one basis, means for producing a first signal indicative of transfer of information to said first asynchronous circuit, means for producing a second signal indicative of said second asynchronous circuit being in a neutral state, said control circuit of said first asynchronous circuits being responsive to said first and second signals to open said gate section of said first asynchronous circuit to transfer information to said second asynchronous circuit, means responsive to transfer of information to said second asynchronous circuit for generating a third signal, said control circuit of said first asynchronous circuit being responsive to said third signal to close said gate section and reset said flip-flop of said first asynchronous circuit to a predetermined state.

Claim 30

An asynchronous system for transmitting information comprising first and second asynchronous circuits each including a control section, a storage section comprising at least one flip-flop, an output gate section and an equal plurality of input and output leads, each said asynchronous circuit establishing signals indicative of information and neutral states, said output gate section being disposed between said storage section and said output leads of its associated asynchronous circuit, output leads of each said asynchronous circuit being connected to input leads of the other of said asynchronous circuit, on a one-for-one basis, means for producing a first signal indicative of transfer of information to said first asynchronous circuit, means for producing a second signal indicative of said second asynchronous circuit being in a neutral state, said control circuit of said first asynchronous circuits being responsive to said first and second signals to open said gate section of said first asynchronous circuit to transfer information to said second asynchronous circuit, means responsive to transfer of information to said second asynchronous circuit for generating a third signal, said control circuit of said first asynchronous circuit being responsive to said third signal to close said gate section and reset said flip-flop of said first asynchronous circuit to a predetermined state.

Claim 31

An asynchronous system for transmitting information comprising first and second asynchronous circuits each including a control section, a storage section for storing information carrying a signals, an output gate section and an equal plurality of input and output leads, each said asynchronous circuit establishing signals indicative of information and neutral states, said output gate section being disposed between said storage section and said output leads of its associated asynchronous circuit, output leads of each said asynchronous circuit being connected to input leads of the other of said asynchronous circuit, and a one-for-one basis, means for producing a first signal indicative of transfer of information to said first asynchronous circuit, means for producing a second signal indicative of said second asynchronous circuit being in a neutral state, said control circuit of said first asynchronous circuits being responsive to said first and second signals to open said gate section of said first asynchronous circuit to transfer information to said second asynchronous circuit, means responsive to transfer of information to said second asynchronous circuit for generating a third signal, said control circuit of said first asynchronous circuit being responsive to said third signal to close said gate section and for establishing in said storage section a predetermined signal.

Claim 32

An asynchronous system for transmitting information comprising first and second asynchronous circuits each including a control section, a storage section for storing information carrying a signals, an output gate section and an equal plurality of input and output leads, each said asynchronous circuit establishing signals indicative of information and neutral states, said output gate section being disposed between said storage section and said output leads of its associated asynchronous circuit, output leads of each said asynchronous circuit being connected to input leads of the other of said asynchronous circuit, and a one-for-one basis, means for producing a first signal indicative of transfer of information to said first asynchronous circuit, means for producing a second signal indicative of said second asynchronous circuit being in a neutral state, said control circuit of said first asynchronous circuits being responsive to said first and second signals to open said gate section of said first asynchronous circuit to transfer information to said second asynchronous circuit, means responsive to transfer of information to said second asynchronous circuit for generating a third signal, said control circuit of said first asynchronous circuit being responsive to said third signal to close said gate section and for establishing in said storage section a predetermined signal.