Carry generation means for multiple character adder

Claim 2

In a stage of a binary adder responsive to input signals comprising the operand signals for that stage and the carry-in signals from previous lower order stages and producing the sum for that stage and a first carry-out signal for a succeeding higher-order stage, the combination comprising: a pattern recognition means responsive to the input signals for producing a control signal when the input signals conform to certain predetermined patterns, and means responsive to the first carry-out signal and said control signal for producing a second carry-out signal from the first carry-out signal in accordance with said control signal.

Claim 3

The combination as recited in claim 1 wherein the second carry-out signal producing means complements the first carry-out signal whenever said control signal is in a first of two states and otherwise produces a second carry-out signal which is the same as the first carry-out signal.

Claim 4

The combination as recited in claim 2 wherein second carry-out signal producing means includes an exclusive OR gate.

Claim 5

In a stage of a three character binary adder responsive to five input signals, comprising three operand signals, a lower order carrier-in signal from the next previous lower order stage, and a higher order carry-in signal from the second previous lower order stage; in combination means for generating the sum for that stage; means for generating a first carry-out signal for one of the next two succeeding higher order stages; and means for generating a second carry-out signal comprising means for complementing the first carry-out signal whenever the five input signals contain at least two binary 1''s and otherwise making the second carry-out signal the same as the first carry-out signal.

Claim 6

In a stage of a three character binary adder responsive to five input signals, comprising three operand signals, a lower order carrier-in signal from the next previous lower order stage, and a higher order carry-in signal from the second previous lower order stage; in combination means for generating the sum for that stage; means for generating a first carry-out signal for one of the next two succeeding higher order stages; and means for generating a second carry-out signal comprising means for complementing the first carry-out signal whenever the five input signals contain at least two binary 1''s and otherwise making the second carry-out signal the same as the first carry-out signal.

Claim 7

The combination as recited in claim 4 wherein said means for generating the second carry-out signal includes: a first logic means responsive to the five input signals for producing a binary 1 signal whenever the five input singals contain at least two binary 1''s and a second logic means responsive to the output of said first logic means and the first carry-out signal for generating the complement of the higher carry-out signal whenever the output of said first logic circuit is a binary 1, and otherwise making the second carry-out signal the same as the first carry-out signal.

Claim 8

The combination as recited in claim 5, wheRein said first logic means includes a threshold gate having a threshold of two.

Claim 9

The combination as recited in claim 5, wherein said second logic means is an exclusive OR gate.

Claim 10

In a stage of a three character binary adder responsive to five input signals, comprising three operand signals, a lower order carry-in signal from the next previous lower order stage, and a higher order carry-in signal from the second previous lower order stage and generating the sum for that stage and a higher order carry-out signal for the second succeeding higher order stage, the combination comprising: a network of AND and OR gates responsive to the five input signals for producing a binary 1 output whenever the five input signals contain at least two binary 1''s, and an exclusive OR gate responsive to the output of said network and to the higher order carry-out signal for producing a lower order carry-out signal for the next succeeding higher order stage.

Claim 11

In a stage of a three character binary adder responsive to five input signals, comprising three operand signals, a lower order carry-in signal from the next previous lower order stage, and a higher order carry-in signal from the second previous lower order stage and generating the sum for that stage and a higher order carry-out signal for the second succeeding higher order stage, the combination comprising: a network of AND and OR gates responsive to the five input signals for producing a binary 1 output whenever the five input signals contain at least two binary 1''s, and an exclusive OR gate responsive to the output of said network and to the higher order carry-out signal for producing a lower order carry-out signal for the next succeeding higher order stage.

Claim 12

In a stage of a three character binary adder responsive to five input signals. comprising three operand signals, a lower order carry-in signal from the next previous lower order stage, and a higher order carry-in signal from the second previous lower order stage, and generating the sum for that stage and a higher order carry-out for the second next higher order stage, the combination comprising: a threshold gate responsive to the five input signals and having a threshold of two for producing a binary 1 output whenever the five input signals contain at least two binary 1''s, and an exclusive OR gate responsive to the output of said threshold gate and to the higher order carry-out signal for producing a lower order carry-out signal to the next succeeding higher order stage.

Claim 13

In a stage of a three character binary adder responsive to five input signals. comprising three operand signals, a lower order carry-in signal from the next previous lower order stage, and a higher order carry-in signal from the second previous lower order stage, and generating the sum for that stage and a higher order carry-out for the second next higher order stage, the combination comprising: a threshold gate responsive to the five input signals and having a threshold of two for producing a binary 1 output whenever the five input signals contain at least two binary 1''s, and an exclusive OR gate responsive to the output of said threshold gate and to the higher order carry-out signal for producing a lower order carry-out signal to the next succeeding higher order stage.