System for providing interrupts in a numerical control system

Claim 2

IN A SYSTEM FOR CONTROLLING A PLURALITY OF EXTERNAL DEVICES WITH A DATA STORAGE DEVICE WHEREIN EACH OF SAID EXTERNAL DEVICES HAS A UNIQUE ADDRESS REPRESENTED BY A STRING OF LOGIC PULSES HAVING SEQUENTIALLY LESSER ADDRESS SIGNIFICANCE AND EACH PULSE BEING EITHER OF TWO LOGIC LEVELS, AN INTERRUPT SYSTEM FOR ENABLING SAID EXTERNAL DEVICES TO INDIVIDUALLY APPLY INTERRUPTING ADDRESS SIGNALS TO SAID DATA STORAGE DEVICE, SAID INTERRUPTING ADDRESS SIGNALS BEING PRESENT WHEN A SELECTED NUMBER OF SAID ADDRESS PULSES IN THE LOWER SIGNIFICANCE POSITIONS ARE AT A SELECTED ONE OF SAID TWO LOGIC STATES, SAID INTERRUPT SYSTEM INCLUDING: FIRST MEANS FOR RECEIVING SAID INTERRUPTING ADDRESS SIGNALS AND AN ENABLE SIGNAL AND PRODUCING AT LEAST ONE INTERRUPT SIGNAL AND AT LEAST ONE RESPONSE SIGNAL; SECOND MEANS FOR RECEIVING ALL OF SAID AT LEAST ONE RESPONSE SIGNALS AND GENERATING SAID ENABLE SIGNAL WHEN ALL OF SAID AT LEAST ONE RESPONSE SIGNALS ARE AT ONE LOGIC LEVEL AND A DISABLE SIGNAL WHEN ANY OF SAID AT LEAST ONE RESPONSE SIGNALS IS AT ANOTHER LOGIC LEVEL SO THAT SAID FIRST MEANS PRODUCES NO OUTPUT SIGNALS WHEN SAID DISABLE SIGNAL IS GENERATED BY SAID SECOND MEANS.

Claim 3

the system of claim 1 wherein said first means for receiving includes a plurality of logic means individually responsive to said interrupting device address signals and said enable signal, a portion of said logic means producing said interrupt when said device interrupting address signals and said enable signals are of the same logic state, and the remainder of said logic means producing said response signals when said enable signal and all of said device address interrupting signals are different.

Claim 4

the system of claim 2 wherein said second means for receiving includes gate means for receiving said response signals and producing said enable signal when all of said response signals are at a logic state different from the logic state of said interrupt address signals and said disable signal when any one of said response signals has a logic state the same as the state of said interrupt address signals.

Claim 5

In a numerical control system for controlling external devices with data from a computer, a system for transmitting device address interrupt signals from an external device to said computer, wherein a plurality of address pulses indicative of the address of an external device is available to said computer in parallel form and said device address interrupt signals are represented by one logic state of said address pulses, said system for transmitting device address interrupt signals comprising: a plurality of logic means equal in number to said plurality of address pulses for individually and simultaneously receiving said pulses; system enable logic means for receiving a system start signal and producing an enable signal, each of said plurality of logic means receiving said enable signal and producing a signal of one logic state when said address pulse and said enable signal are the same as said one logic state, and a signal of another logic state for all other combinations of logic states of said address pulses and said enable signal; enable signal retention means responsive to a first portion of said plurality of logic means for actuating said system enable logic means when said first portion of said plurality of logic means all yield an output different from said one logic state and for disabling said first portion of logic means for other combination of said address pulses and said outputs, the remainder of said plurality of logic means also receiving said enable signal to produce said interrupt signals when said enable signal and said aDdress pulses are the same logic state, said remainder of said logic means receiving the address pulses of the lesser significance.

Claim 6

In a numerical control system for controlling external devices with data from a computer, a system for transmitting device address interrupt signals from an external device to said computer, wherein a plurality of address pulses indicative of the address of an external device is available to said computer in parallel form and said device address interrupt signals are represented by one logic state of said address pulses, said system for transmitting device address interrupt signals comprising: a plurality of logic means equal in number to said plurality of address pulses for individually and simultaneously receiving said pulses; system enable logic means for receiving a system start signal and producing an enable signal, each of said plurality of logic means receiving said enable signal and producing a signal of one logic state when said address pulse and said enable signal are the same as said one logic state, and a signal of another logic state for all other combinations of logic states of said address pulses and said enable signal; enable signal retention means responsive to a first portion of said plurality of logic means for actuating said system enable logic means when said first portion of said plurality of logic means all yield an output different from said one logic state and for disabling said first portion of logic means for other combination of said address pulses and said outputs, the remainder of said plurality of logic means also receiving said enable signal to produce said interrupt signals when said enable signal and said aDdress pulses are the same logic state, said remainder of said logic means receiving the address pulses of the lesser significance.

Claim 7

The system of claim 4 wherein said address pulses are applied to said remainder of said logic means at a first logic state, and said enable signal is at said first logic state so that said interrupt pulses are produced at said first logic state, and said address pulses are applied to said first portion of said logic means at a second logic state; and wherein said enable signal retention means includes gate means for producing said enable signal at said first logic state when all of said address pulses applied to said first portion of said logic means are at said second logic state, and said enable signal retention means disables said system for transmitting interrupt signals when any one of said address pulses to said first portion of said logic means becomes said first state.

Claim 8

The system of claim 4 wherein said enable signal retention means includes first gate means responsive to said first portion of said plurality of logic means and producing an output of said one logic state when said address pulses and said enable signal are said one logic state, and producing an output of said other logic state; and logic means for receiving and inverting the output of said first gate means to thereby provide said enable signal when said address pulses and said enable signal are different.