Patent US3755746A successfully refreshed from Google Patents.
US3755746A
Expired / Lapsed
US
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Frequency comparison indicating apparatus
Assignee: Collins Radio Co
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Filing: 1972-03-07
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Granted: 1973-08-28
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Expires: 1992-03-07
Abstract
Abstract A gating system for use with a frequency discriminator which will provide a positive indication of whether or not two input signals are the same frequency or, if they are not the same frequency, which one is the higher. The apparatus is for use with a frequency detector providing logic ''''1'''' and logic ''''0'''' outputs indicative of the highest frequency and providing an alternating output when the two frequencies are identical. The output of the frequency discriminator is utilized to steer flipflops to provide the necessary positive outputs.
Inventors
- 👤 N Hogue
- 👤 C Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:08
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
247 words
Apparatus as the class described comprising, in combination: signal supply first means for supplying first and second signals representative of first and second frequencies, respectively; first detection means, including first and second inputs and first and second outputs, connected to said signal supply first means for receiving said first and second signals therefrom, said first detection means supplying a substantially continuous first logic level at said first output when said first signal as received is a higher frequency than said second signal and supplying the opposite, substantially continuous second logic level at said first output when said first frequency is lower than said second frequency, said first output supplying an alternating signal when said first and second signals are of the same frequency and said second output supplying a logic level which is the same frequency but inverted with respect to the logic level of the signal supplied at said first output; and second detection means connected to said output means of said first detection means and to said signal supply first means, said second detection means including first, second, and third output means, a given logic level appearing at only one of said first, second, and third outputs at a given time and said logic level being indicative, respectively, of the first signal being of a higher frequency than said second signal, said first signal being equal in frequency to said second signal and the first signal being of a lower frequency than said second signal.
Claim 2
Dependent Claim
247 words
Apparatus as the class described comprising, in combination: signal supply first means for supplying first and second signals representative of first and second frequencies, respectively; first detection means, including first and second inputs and first and second outputs, connected to said signal supply first means for receiving said first and second signals therefrom, said first detection means supplying a substantially continuous first logic level at said first output when said first signal as received is a higher frequency than said second signal and supplying the opposite, substantially continuous second logic level at said first output when said first frequency is lower than said second frequency, said first output supplying an alternating signal when said first and second signals are of the same frequency and said second output supplying a logic level which is the same frequency but inverted with respect to the logic level of the signal supplied at said first output; and second detection means connected to said output means of said first detection means and to said signal supply first means, said second detection means including first, second, and third output means, a given logic level appearing at only one of said first, second, and third outputs at a given time and said logic level being indicative, respectively, of the first signal being of a higher frequency than said second signal, said first signal being equal in frequency to said second signal and the first signal being of a lower frequency than said second signal.
Claim 3
Dependent Claim
238 words
Apparatus as claimed in claim 1 wherein said second detecting means comprises, in combination: first and second NAND gates each having first and second inputs and an output; first and second RS flip-flop means each including R and S inputs, clock inputs and true and false outputs; means connecting said first output of said first detection means to said first input of said NAND gate and said second output of said first detection means to said first input of said second NAND gate; means connecting the output of said first NAND gate to said R input of said first flip-flop, said S input of said second flip-flop and said second input of said second NAND gate; means connecting said output of said second NAND gate to said R input of said second flip-flop, said S input of said first flip-flop and said second input of said first NAND gate; means connecting said signal supply first means to said flip-flop means whereby said first signal is supplied to the clock input of said first flip-flop and said second signal is supplied to said clock input of said second flip-flop; means connecting said false outputs of said first and second flip-flops, respectively, to said first and third outputs of said second detection means, respectively; and means supplying the logical AND of said true outputs of said first and second flip-flops to said second output means of said second detection means.
Claim 4
Dependent Claim
232 words
Apparatus of the class described comprising, in combination: first and second NAND gate means each including first and second input means and output means; AND gate means including first and second input means and output means; steered first and second flip-flop means each including set and reset inputs, true and false outputs and clocking inputs; first and second steering input signal supplying means; means connecting said first and second steering input signal supplying means to said clock inputs of said first and second flip-flops respectively; means connecting said output means of said first NAND gate means to the first input of said second NAND gate means, to the reset input of said first flip-flop means and to the set input of said second flip-flop means; means connecting the output of said second NAND gate means to the first input of said first NAND gate means, the set input of said first flip-flop means and the reset input of said second flip-flop means; means connecting the true outputs of said first and second flip-flop means to the first and second inputs of said AND gate means; first and second logic level signal supplying means connected to the second input means of said first and second NAND gate means, respectively; and output means connected to the output means of said AND gate means and to the false outputs of said first and second flip-flops.
Claim 5
Dependent Claim
232 words
Apparatus of the class described comprising, in combination: first and second NAND gate means each including first and second input means and output means; AND gate means including first and second input means and output means; steered first and second flip-flop means each including set and reset inputs, true and false outputs and clocking inputs; first and second steering input signal supplying means; means connecting said first and second steering input signal supplying means to said clock inputs of said first and second flip-flops respectively; means connecting said output means of said first NAND gate means to the first input of said second NAND gate means, to the reset input of said first flip-flop means and to the set input of said second flip-flop means; means connecting the output of said second NAND gate means to the first input of said first NAND gate means, the set input of said first flip-flop means and the reset input of said second flip-flop means; means connecting the true outputs of said first and second flip-flop means to the first and second inputs of said AND gate means; first and second logic level signal supplying means connected to the second input means of said first and second NAND gate means, respectively; and output means connected to the output means of said AND gate means and to the false outputs of said first and second flip-flops.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-27 | 1977-02-26 | 1977-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-27 | 1981-02-26 | 1981-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-27 | 1985-02-26 | 1985-08-28 | $7700.00 | Window Closed / Lapsed |