Resistor isolation for double mesa transistors

Claim 2

A high voltage and high current integrated circuit of cascaded common collector mesa emitter transistors and bleeder resistors that resists secondary breakdown comprising a wafer of a high resistivity semiconductive material of one conductivity type having two major faces and a circumferential edge surface between said faces, a first lower resistivity stratum in said wafer of said one conductivity type coextensive with one wafer face and intersecting said edge surface, a second stratum in said wafer coextensive with the opposite wafer face, said second stratum of opposite conductivity type and intersecting said edge surface, first and second mesas of said one conductivity type semiconductive material on said second stratum, first and second mutually spaced lower resistivity surface regions of said opposite conductivity type in said second stratum, said first mesa disposed between said first and second lower resistivity surface regions, said second lower resistivity surface region surrounding said second mesa, a first electrode on said first lower resistivity surface region, a second electrode on both said first mesa and said second lower resistivity surface region providing an integral bleeder resistor for said first mesa through said second stratum between said lower resistivity surface regions, a third electrode on both said second mesa and a portion of said second lower resistivity surface region, said second and third electrodes being spaced on said second lower resistivity surface region to provide an integral bleeder resistor for said second mesa along a surface portion of said second lower resistivity surface region, a fourth electrode on the first stratum of said one wafer face, and separate terminal connections, respectively, to said first, third and fourth electrodes serving as base, emitter and collector connections.

Claim 3

A high voltage and high current integrated circuit of cascaded common collector mesa emitter transistors and bleeder resistors that resists secondary breakdown comprising a wafer of a high resistivity silicon of one conductivity type having two major faces and a circumferential edge surface betwen said faces, a first lower resistivity stratum in said wafer of said one conductivity type coextensive with one wafer face and intersecting said edge surface, a second stratum in said wafer coextensive with the opposite wafer face, said second stratum of opposite conductivity type and intersecting said edge surface, first and second mesas of said one conductivity type silicon on said second stratum, first and second lower resistivity surface regions of said opposite conductivity type in said second stratum, said first mesa disposed between said first and second lower resistivity surface regions, said second lower resistivity surface region surrounding said second mesa, a first electrode on said first lower resistivity surface region, a second electrode on both said first mesa and said second lower resistivity surface region providing an integral bleeder resistor for said first mesa through said second stratum between said lower resistivity surface regions, a third electrode on both said second mesa and a portion of said second lower resistivity surface region adjacent a side of said second mesa opposite said first mesa, said second and third electrodes being laterally spaced a predetermined distance to provide an integral bleeder resistor for said second mesa along a surface portion of said second lower resistivity surface region, a fourth electrode on said first stratum of said one wafer face, an etch moat on said opposite wafer face spaced inwardly from from said edge surface and circumscribing said mesas, regions, and electrodes, said etch moat spaced outwardly from said mesas and extending down entirely through said second stratum, and separate terminal connections, respectively, to said first, third and fourth electrodes serving as base, emitter and collector connections.

Claim 4

A high voltage and high current integrated circuit of cascaded common collector mesa emitter transistors and bleeder resistors that resists secondary breakdown comprising a wafer of a high resistivity silicon of one conductivity type having two major faces and a circumferential edge surface betwen said faces, a first lower resistivity stratum in said wafer of said one conductivity type coextensive with one wafer face and intersecting said edge surface, a second stratum in said wafer coextensive with the opposite wafer face, said second stratum of opposite conductivity type and intersecting said edge surface, first and second mesas of said one conductivity type silicon on said second stratum, first and second lower resistivity surface regions of said opposite conductivity type in said second stratum, said first mesa disposed between said first and second lower resistivity surface regions, said second lower resistivity surface region surrounding said second mesa, a first electrode on said first lower resistivity surface region, a second electrode on both said first mesa and said second lower resistivity surface region providing an integral bleeder resistor for said first mesa through said second stratum between said lower resistivity surface regions, a third electrode on both said second mesa and a portion of said second lower resistivity surface region adjacent a side of said second mesa opposite said first mesa, said second and third electrodes being laterally spaced a predetermined distance to provide an integral bleeder resistor for said second mesa along a surface portion of said second lower resistivity surface region, a fourth electrode on said first stratum of said one wafer face, an etch moat on said opposite wafer face spaced inwardly from from said edge surface and circumscribing said mesas, regions, and electrodes, said etch moat spaced outwardly from said mesas and extending down entirely through said second stratum, and separate terminal connections, respectively, to said first, third and fourth electrodes serving as base, emitter and collector connections.

Claim 5

A high voltage and high current integrated circuit of cascaded common collector mesa emitter transistors and bleeder resistors that resists secondary breakdown comprising a wafer of high resistivity N-type silicon having two major faces and a circumferential edge surface between said faces, a stratum of P-type silicon coextensive with one face of said wafer and intersecting said edge surface, a first elongated mesa of N-type silicon extending across said wafer face on said P-type stratum dividing said face into first and second P-type portions, a second mesa of N-type silicon on said wafer face wholly within said second P-type portion, a diffused P-type surface enhancement layer throughout the face of said P-type stratum except beneath said mesas, a first electrode on said first P-type portion, a second electrode having a part on said first mesa and a part on said second P-type portion providing a bleeder resistor for said first mesa through said P-type stratum under said first mesa, the part of said second electrode on said second P-type portion extending around and partially encircling said second mesa, a third electrode having a part on said second mesa and a part on said second P-type portion on a side of said second mesa opposite from said first mesa, said second and third electrodes being laterally spaced on said second P-type portion to provide an integral bleeder resistor along the surface of said second P-type, an etch moat on said one wafer face spaced inwardly from said edge surface, and circumscribing said mesas, portions, and electrodes, said etch moat contacting opposite ends of said first mesa and extending down entirely through said P-type stratum of low resistivity N-type silicon coextensive with the opposite face of said wafer, a fourth electrode on said opposite face of said wafer, and separate terminal connections, respectively, to said first, third and fourth electrodes serving as base, emitter and collector terminal connections.

Claim 6

A high voltage and high current integrated circuit of cascaded common collector mesa emitter transistors and bleeder resistors that resists secondary breakdown comprising a wafer of high resistivity N-type silicon having two major faces and a circumferential edge surface between said faces, a stratum of P-type silicon coextensive with one face of said wafer and intersecting said edge surface, a first elongated mesa of N-type silicon extending across said wafer face on said P-type stratum dividing said face into first and second P-type portions, a second mesa of N-type silicon on said wafer face wholly within said second P-type portion, a diffused P-type surface enhancement layer throughout the face of said P-type stratum except beneath said mesas, a first electrode on said first P-type portion, a second electrode having a part on said first mesa and a part on said second P-type portion providing a bleeder resistor for said first mesa through said P-type stratum under said first mesa, the part of said second electrode on said second P-type portion extending around and partially encircling said second mesa, a third electrode having a part on said second mesa and a part on said second P-type portion on a side of said second mesa opposite from said first mesa, said second and third electrodes being laterally spaced on said second P-type portion to provide an integral bleeder resistor along the surface of said second P-type, an etch moat on said one wafer face spaced inwardly from said edge surface, and circumscribing said mesas, portions, and electrodes, said etch moat contacting opposite ends of said first mesa and extending down entirely through said P-type stratum of low resistivity N-type silicon coextensive with the opposite face of said wafer, a fourth electrode on said opposite face of said wafer, and separate terminal connections, respectively, to said first, third and fourth electrodes serving as base, emitter and collector terminal connections.

Claim 7

A high voltage and high current integrated circuit of cascaded common collector mesa emitter transistors and bleeder resistors that resists secondary breakdown comprising a wafer of a high resistivity N-type silicon having two major faces and a circumferential edge surface, a P-type diffused layer coextensive with one face of said wafer and intersecting said edge surface, first and second N-type silicon mesas on said P-type diffused layer, first and second lower resistivity diffused P-type regions in surface portions of said P-type layer, at least part of said first mesa disposed between said first and second lower resistivity diffused P-type regions, said second lower resistivity P-type region surrounding said second mesa, a first evaporated aluminum electrode on said first lower resistivity diffused P-type region, a second evaporated aluminum elecTrode having a part on said first mesa and a part on said second lower resistivity diffused P-type region providing an integral bleeder resistor for said first mesa between said lower resistivity diffused P-type regions through said P-type layer, the part of said second electrode on said second diffused P-type region extending around and at least partially encircling said second mesa, a third evaporated aluminum electrode having a part on both said second mesa and a part on said second lower resistivity diffused P-type region on a side of said second mesa opposite from said first mesa, said second and third electrodes being laterally spaced a predetermined distance to provide an integral bleeder resistor for said second mesa along a surface portion of said second lower resistivity diffused P-type region, an etch moat on said opposite wafer spaced inwardly from said edge surface and circumscribing said mesas, regions, and electrodes, said etch moat extending down entirely through said diffused P-type layer, a lower resistivity diffused N-type layer coextensive with the opposite one face and intersecting said edge surface, a fourth electrode on said lower resistivity diffused N-type layer, and separate terminal connections, respectively, to said first, third and fourth electrodes serving as base, emitter and collector connections.

Claim 8

A high voltage and high current integrated circuit of cascaded common collector mesa emitter transistors and bleeder resistors that resists secondary breakdown comprising a wafer of a high resistivity N-type silicon having two major faces and a circumferential edge surface, a P-type diffused layer coextensive with one face of said wafer and intersecting said edge surface, first and second N-type silicon mesas on said P-type diffused layer, first and second lower resistivity diffused P-type regions in surface portions of said P-type layer, at least part of said first mesa disposed between said first and second lower resistivity diffused P-type regions, said second lower resistivity P-type region surrounding said second mesa, a first evaporated aluminum electrode on said first lower resistivity diffused P-type region, a second evaporated aluminum elecTrode having a part on said first mesa and a part on said second lower resistivity diffused P-type region providing an integral bleeder resistor for said first mesa between said lower resistivity diffused P-type regions through said P-type layer, the part of said second electrode on said second diffused P-type region extending around and at least partially encircling said second mesa, a third evaporated aluminum electrode having a part on both said second mesa and a part on said second lower resistivity diffused P-type region on a side of said second mesa opposite from said first mesa, said second and third electrodes being laterally spaced a predetermined distance to provide an integral bleeder resistor for said second mesa along a surface portion of said second lower resistivity diffused P-type region, an etch moat on said opposite wafer spaced inwardly from said edge surface and circumscribing said mesas, regions, and electrodes, said etch moat extending down entirely through said diffused P-type layer, a lower resistivity diffused N-type layer coextensive with the opposite one face and intersecting said edge surface, a fourth electrode on said lower resistivity diffused N-type layer, and separate terminal connections, respectively, to said first, third and fourth electrodes serving as base, emitter and collector connections.