US3755695A — Solid state motor control cycling timer

Claim 1

Independent Claim 267 words

A solid state timer for repetitively connecting and disconnecting an a.c. source to a load in a cyclical manner comprising: first means coupled across said source for developing a regulated d.c. output; first and second voltage detector means each having anode, gate and cathode electrodes; said cathode electrodes being coupled to one terminal of said source; first and second voltage reference circuits coupled between said d.c. output and the gate electrodes of their associated voltage detector means for establishing a constant voltage reference level at the gates of their associated voltage detector means; firs and second timing circuits each being coupled between said d.c. output and the anode electrodes of their associated voltage detector mens to turn their associated voltage detectors on when the voltage at the output of the timing circuit exceeds the reference level; said first and second voltage reference circuits each having a time delay element, the time delay element of said first voltage reference circuit having a greater time delay value than the time delay element of said second voltage reference circuit to cause said second voltage reference circuit to reach its reference level before said first voltage reference circuit reaches its reference level; solid state switch means being coupled in series with said soruce and said load; said switch means having a control electrode; means coupled between said second voltage reference circuit and said control electrode for controlling the state of said switch means whereby said switch means always begins operation in a conductive state when said source is activated due to the time delay elements employed in said voltage reference circuits.

Claim 2

Dependent Claim 267 words

A solid state timer for repetitively connecting and disconnecting an a.c. source to a load in a cyclical manner comprising: first means coupled across said source for developing a regulated d.c. output; first and second voltage detector means each having anode, gate and cathode electrodes; said cathode electrodes being coupled to one terminal of said source; first and second voltage reference circuits coupled between said d.c. output and the gate electrodes of their associated voltage detector means for establishing a constant voltage reference level at the gates of their associated voltage detector means; firs and second timing circuits each being coupled between said d.c. output and the anode electrodes of their associated voltage detector mens to turn their associated voltage detectors on when the voltage at the output of the timing circuit exceeds the reference level; said first and second voltage reference circuits each having a time delay element, the time delay element of said first voltage reference circuit having a greater time delay value than the time delay element of said second voltage reference circuit to cause said second voltage reference circuit to reach its reference level before said first voltage reference circuit reaches its reference level; solid state switch means being coupled in series with said soruce and said load; said switch means having a control electrode; means coupled between said second voltage reference circuit and said control electrode for controlling the state of said switch means whereby said switch means always begins operation in a conductive state when said source is activated due to the time delay elements employed in said voltage reference circuits.

Claim 3

Dependent Claim 157 words

The solid state timer of claim 1 wherein said first and second timing circuits are each comprised of a capacitor and an adjustable variable resistance means; a common resistance means being coupled between said d.c. output and one terminal of the capacitors in said first and second timing circuits; said variable resistance means each being coupled between said d.c. output and the remaining terminal of their assocaited capacitor; the common terminal between each capacitor and its associated variable resistance means being coupled to the anodeof its assocaited voltage detector means; the capacitors of said first and second timing circuits being connected in series between the anodes of said first and second voltage detectors to abruptly turn off the voltage detector which was previously turned on when the capacitor associated with the voltage detector in the off state is charged to a voltage level which exceeds the reference level applied to the gate of its associated voltage detector.

Claim 4

Dependent Claim 27 words

The solid state timer of claim 1 wherein said voltage detectors are each comprised of a programmable unijunction transistor having an anode gate and a cathode electrode.

Claim 5

Dependent Claim 42 words

The solid state timer of claim 2 further comprising first and second diodes each coupled between said d.c. output and the common terminals of their associated timing circuits for rapidly discharging the timing circuit capacitors whenever said source is removed or deactivated.

Claim 6

Dependent Claim 59 words

The solid state timing circuit of claim 1 further comprising diode means coupled to said cathode of the coltage detector means associated with said second voltage circuit to compensate for any residual charge remaining in the capacitor or the timing circuit associated with said second voltage reference circuit and thereby prevent this voltage detector means from turning on first.

Claim 7

Dependent Claim 81 words

The solid state timer of claim 1 wherein said control means is comprised of emitter follower means which is adapted to turn said solid state switch on when said emitter follower means is turned off and vice versa; diode means coupled between the control electrode of said solid state switch and said emitter follower means to provide a threshold level sufficient to prevent said control means for erroneously turning said solid state switch on when said emitter follower means is conducting.

Claim 8

Dependent Claim 31 words

The solid state timer of claim 1 further comprising a resistor and a capacitor connected in series across the solid state switch to prevent erroneous re-triggering of the solid state switch.

Claim 9

Dependent Claim 15 words

The solid state timer of claim 1 wherein said solid state switch is a triac.

Claim 10

Dependent Claim 47 words

The solid state timer of claim 1 wherein said voltage reference circuits are each comprised of at least first and second resistors coupled in series across said d.c. output and said one source terminal; said timing elements being capacitors coupled in parallel across one of said resistors.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1976-08-27	1977-02-26	1977-08-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1980-08-27	1981-02-26	1981-08-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1984-08-27	1985-02-26	1985-08-28	$7700.00	Window Closed / Lapsed

Solid state motor control cycling timer

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