Time delay circuit adapted for use in a power control system

Claim 2

In a power control system for providing a power signal which varies in response to an input signal so as to control the power being supplied to a load, a time delay circuit for effecting a predetermined time delay between initiation of the input signal and the signal supplying power to the load, said time delay circuit comprising: a time delay network including an interconnected resistor and capacitor, means coupled to said capacitor for maintaining a preset voltage thereacross at the initiation of a charging cycle and at the completion of a discharging cycle, means coupled to said time delay network for charging said capacitor in response to initiation of the input signal until a preselected voltage level in excess of said preset level appears across said capacitor in a predetermined time interval, said predetermined time interval varying in response to the value of said preselected voltage level, voltage sensitive switch means coupled to said capacitor, said voltage sensitive switch means being rendered conductive in response to the establishment of said preselected voltage level to provide a discharge path for said capacitor, a selectively adjustable bias means coupled to said voltage sensitive switch means for controlling the conduction of said voltage sensitive switch means by maintaining said voltage sensitive switch means in a nonconductive state until said preselected voltage level is established across said capacitor so as to control said predetermined time interval in response to the adjustment of said selectively adjustable bias means, means coupled to said capacitor discharge path to provide an output signal in response to the discharge of said capacitor upon the expiration of said predetermined time interval, output switch means coupled to the load, and means for coupling said output signal to said output switch means so as to control the conduction of said output switch means and thereby control the supply of power to the load.

Claim 3

In a power control system in accordance with claim 1 wherein said voLtage sensitive switch means comprises a first transistor having a base, collector, and emitter, said selectively adjustable bias means being coupled to said base of said first transistor for maintaining said first transistor nonconductive during said predetermined time interval set by the adjustment of said selectively adjustable bias means, a second transistor having a base, collector, and emitter, said second transistor being coupled to said first transistor and being rendered conductive in response to conduction of said first transistor, and an output resistor connected to said second transistor for providing an output voltage signal in response to conduction of said second transistor, wherein means are coupled to said first transistor for supplying a latching signal subsequent to the discharge of said capacitor for maintaining said first transistor in a conductive state until said output switch means is rendered nonconductive, and wherein said output switch means includes a shunt transistor connected to said output resistor and adapted to be rendered conductive in response to said output voltage signal.

Claim 4

In a power control system in accordance with claim 2 wherein a reed relay switch is provided coupled to said shunt transistor, said reed relays switch including a pair of contacts operatively connected thereto and being adapted to control the supply of power to the load.

Claim 5

In a power control system in accordance with claim 2 wherein said first transistor comprises a PNP transistor having its emitter coupled to said capacitor so that the level of the bias voltage maintained at its base in response to the selected adjustment of said selectively adjustable bias means controls the value of the preselected voltage level established across the capacitor for initiating conduction of said first transistor, said first transistor having its collector coupled to the base of said second transistor so as to supply a base signal thereto, said second transistor comprises an NPN transistor having its collector coupled to said bias means and having its emitter coupled to said output resistor, said output switch means includes a selectively energizable switch, and said shunt transistor comprises an NPN transistor having its base emitter junction connected across said output resistor and having its collector connected to said selectively energizable switch so as to control the operation of said selectively energizable switch in response to conduction of said NPN shunt transistor.

Claim 6

A time delay circuit for effecting a predetermined time delay between an input signal and the initiation of an output signal which controls the power being supplied to a load comprising: an interconnected resistor and capacitor comprising a time delay network, said capacitor being adapted to be charged to a preselected voltage level, a pedestal network coupled to said time delay network for establishing a preset voltage across said capacitor at the initiation of a charging cycle and at the completion of a discharging cycle, an input switch means coupled to said time delay network for initiating a charging cycle and a discharging cycle in a preselected time interval upon closure thereof in response to the input signal, said preselected time interval varying in response to the value of said preselected voltage level, a voltage sensitive switch transistor coupled to said capacitor, said voltage sensitive switch transistor being rendered conductive in response to the establishment of said preselected voltage level across said capacitor so as to comprise a portion of a discharge path for said capacitor, selectively adjustable means coupled to said voltage sensitive switch transistor and to said capacitor for biasing said voltage sensitive switch transistor so as to selectively adjust the value of said preselected voltage level to which said capacitor is charged and so as to selectively control said predetermined time interval in accordance with the selected value of said pReselected voltage level, a current responsive switch transistor coupled to said voltage sensitive switch transistor, said current responsive switch transistor being rendered conductive in response to conduction of said voltage sensitive switch transistor and comprising another portion of the discharge path for said capacitor, an output switch transistor coupled to said current responsive switch transistor, said output switch transistor being rendered conductive in response to conduction of said current responsive transistor, a selectively energizable relay connected to said output transistor, said relay including a relay coil serially connected to said output transistor and including a pair of contacts which upon closure in response to energization of said relay coil initiates the supply of power to the load.

Claim 7

A time delay circuit for effecting a predetermined time delay between an input signal and the initiation of an output signal which controls the power being supplied to a load comprising: an interconnected resistor and capacitor comprising a time delay network, said capacitor being adapted to be charged to a preselected voltage level, a pedestal network coupled to said time delay network for establishing a preset voltage across said capacitor at the initiation of a charging cycle and at the completion of a discharging cycle, an input switch means coupled to said time delay network for initiating a charging cycle and a discharging cycle in a preselected time interval upon closure thereof in response to the input signal, said preselected time interval varying in response to the value of said preselected voltage level, a voltage sensitive switch transistor coupled to said capacitor, said voltage sensitive switch transistor being rendered conductive in response to the establishment of said preselected voltage level across said capacitor so as to comprise a portion of a discharge path for said capacitor, selectively adjustable means coupled to said voltage sensitive switch transistor and to said capacitor for biasing said voltage sensitive switch transistor so as to selectively adjust the value of said preselected voltage level to which said capacitor is charged and so as to selectively control said predetermined time interval in accordance with the selected value of said pReselected voltage level, a current responsive switch transistor coupled to said voltage sensitive switch transistor, said current responsive switch transistor being rendered conductive in response to conduction of said voltage sensitive switch transistor and comprising another portion of the discharge path for said capacitor, an output switch transistor coupled to said current responsive switch transistor, said output switch transistor being rendered conductive in response to conduction of said current responsive transistor, a selectively energizable relay connected to said output transistor, said relay including a relay coil serially connected to said output transistor and including a pair of contacts which upon closure in response to energization of said relay coil initiates the supply of power to the load.

Claim 8

A time delay circuit for effecting a predetermined time delay between the initiation of an input signal and the production of an output signal which controls the power being supplied to a load comprising: an interconnected resistor and capacitor comprising a time delay network, said capacitor being adapted to be charged to a preselected voltage level in a predetermined time interval, a pedestal network coupled to said time delay network for establishing a preset voltage across said capacitor prior to the initiation of a charging cycle and at the completion of a discharging cycle, means coupled to said time delay network for initiating charging of said capacitor to said preselected voltage level, a voltage sensitive switch transistor coupled to said capacitor, said voltage sensitive switch transistor being rendered conductive in response to the establishment of said preselected voltage level across said capacitor so as to comprise a portion of a discharge path for said capacitor, means for controlling the magnitude of said preselected voltage level including a selectively adjustable bias means coupled to said voltage sensitive switch transistor for adjusting the voltage level at which said voltage sensitive switch transistor is rendered conductive so as to control the magnitude of said preselected voltage level and thereby control said time interval required for said capacitor to be charged to said preselected voltage level, an energizing transitor coupled to said voltage sensitive switch transistor, said energizing transistor being rendered conductive in response to conduction of said voltage sensitive switch transistor and comprising another portion of the discharge path for said capacitor, a shunt transistor coupled to said energizing transistor, said shunt transitor being rendered conductive in response to conduction of said energizing transistor, a switch transistor having its input connected across the output of said shunt transistor in a manner so that conduction of said shunt transistor is effective to shunt the input of said switch transistor and render said switch transistor nonconductive in response to conduction of said shunt transistor, a selectively energizable relay connected to said switch transistor, said relay including a relay coil serially connected to said switch transistor and including a pair of contacts which, upon opening in response to deenergization of said relay coil as a result of nonconduction of said switch transistor, initiate the disruption of the supply of power to the load.

Claim 9

A time delay circuit for effecting a predetermined time delay between the initiation of an input signal and the production of an output signal which controls the power being supplied to a load comprising: an interconnected resistor and capacitor comprising a time delay network, said capacitor being adapted to be charged to a preselected voltage level in a predetermined time interval, a pedestal network coupled to said time delay network for establishing a preset voltage across said capacitor prior to the initiation of a charging cycle and at the completion of a discharging cycle, means coupled to said time delay network for initiating charging of said capacitor to said preselected voltage level, a voltage sensitive switch transistor coupled to said capacitor, said voltage sensitive switch transistor being rendered conductive in response to the establishment of said preselected voltage level across said capacitor so as to comprise a portion of a discharge path for said capacitor, means for controlling the magnitude of said preselected voltage level including a selectively adjustable bias means coupled to said voltage sensitive switch transistor for adjusting the voltage level at which said voltage sensitive switch transistor is rendered conductive so as to control the magnitude of said preselected voltage level and thereby control said time interval required for said capacitor to be charged to said preselected voltage level, an energizing transitor coupled to said voltage sensitive switch transistor, said energizing transistor being rendered conductive in response to conduction of said voltage sensitive switch transistor and comprising another portion of the discharge path for said capacitor, a shunt transistor coupled to said energizing transistor, said shunt transitor being rendered conductive in response to conduction of said energizing transistor, a switch transistor having its input connected across the output of said shunt transistor in a manner so that conduction of said shunt transistor is effective to shunt the input of said switch transistor and render said switch transistor nonconductive in response to conduction of said shunt transistor, a selectively energizable relay connected to said switch transistor, said relay including a relay coil serially connected to said switch transistor and including a pair of contacts which, upon opening in response to deenergization of said relay coil as a result of nonconduction of said switch transistor, initiate the disruption of the supply of power to the load.