US3755691A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Keyboard clock with timing circuitry for controlling transfer of data between keyboard and processing apparatus
Assignee: Magsat Corp
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Filing: 1972-06-09
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Granted: 1973-08-28
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Expires: 1992-06-09
Abstract
Abstract A timing circuit for sensing the operative condition of keyboard actuated switches and for generating, in the proper sequence, control signals for devices employed to temporarily store input data and further control signals for informing processing equipment that data has been entered in the keyboard. The invention also provides for the generation of a ''''break through'''' or repeat function.
Inventors
- 👤 A Cassarino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:38
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/02
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
132 words
A timing circuit comprising: means responsive to a pair of simultaneously generated short duration input signals for generating a timing pulse having a duration greater than said input signals; means responsive to said timing pulse for imparting a preselected delay thereto; first means responsive to the timing pulse and the delayed timing pulse for generating first and second control pulses synchronized respectively with the leading and trailing edges of the timing pulse, the duration of said first and second control pulses being equal to the delay imparted to the timing pulse; and second means responsive to the timing pulse and to the delayed timing pulse for generating a third control pulse having a duration commensurate with the time between termination of the first control pulse and generation of the second control pulse.
Claim 2
Dependent Claim
132 words
A timing circuit comprising: means responsive to a pair of simultaneously generated short duration input signals for generating a timing pulse having a duration greater than said input signals; means responsive to said timing pulse for imparting a preselected delay thereto; first means responsive to the timing pulse and the delayed timing pulse for generating first and second control pulses synchronized respectively with the leading and trailing edges of the timing pulse, the duration of said first and second control pulses being equal to the delay imparted to the timing pulse; and second means responsive to the timing pulse and to the delayed timing pulse for generating a third control pulse having a duration commensurate with the time between termination of the first control pulse and generation of the second control pulse.
Claim 3
Dependent Claim
34 words
The apparatus of claim 1 further comprising: first gate means responsive to said timing pulse for preventing application of input signals to said timing pulse generating means during the duration of said timing pulses.
Claim 4
Dependent Claim
49 words
The apparatus of claim 1 wherein said timing pulse generating means comprises: logic circuit means responsive to a pair of simultaneously generated input signals for providing a first gating signal; and monostable multivibrator means responsive to gating signals provided by said logic circuit means for generating a timing pulse.
Claim 5
Dependent Claim
35 words
The apparatus of claim 3 further comprising: first gate means responsive to said timing pulses for preventing application of said first gating signals to said monostable multivibratoR means during the duration of said timing pulses.
Claim 6
Dependent Claim
44 words
The apparatus of claim 3 further comprising: gate means responsive to the trailing edge of the delayed timing pulses and to said first gating signals for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means.
Claim 7
Dependent Claim
45 words
The apparatus of claim 4 further comprising: second gate means responsive to the trailing edge of the delayed timing pulses and to said first gating signal for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means.
Claim 8
Dependent Claim
79 words
The apparatus of claim 4 wherein said first means responsive to the timing pulses and to the delayed timing pulses comprises: means for inverting the timing pulses generated by said monostable multivibrator means; means responsive to the inverted timing pulses and to the delayed timing pulses for generating said first control pulses; means for inverting the delayed timing pulses; and means responsive to said timing pulses and to said inverted delayed timing pulses for generating said second control pulses.
Claim 9
Dependent Claim
45 words
The apparatus of claim 7 further comprising: second gate means responsive to the trailing edge of the delayed timing pulse and to said first gating signal for repetitively triggering said monostable multivibrator means upon application of steady state input signals to said logic circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-27 | 1977-02-26 | 1977-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-27 | 1981-02-26 | 1981-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-27 | 1985-02-26 | 1985-08-28 | $7700.00 | Window Closed / Lapsed |