Method for directly measuring the distance travelled over by a vehicle moving in a water body, with respect to the submerged ground surface and device therefor

Claim 3

A method according to claim 1 wherein the ratio is a positive whole power of number two.

Claim 4

A method according to claim 1 comprising multiplying before the measuring step the difference between the accrued whole number of periods with a predetermined factor so as to divide by the same factor the relative error in the measured value of the distance.

Claim 9

A device according to claim 5 wherein the combining means produces signals at a frequency equal to the product of the difference between the respective frequencies of the received wave trains and the transmitted wave trains, by factor 2n, n being a positive integer and the means for computing the distance comprises two adding-subtracting binary counters coupled in series one of which has n bits.

Claim 10

A device according to claim 5 wherein the means for combining produce two signals at frequencies equal to the product of said frequency differences by the same factor 2n, n being a positive integer, and the computation means comprise two binary adding-subtracting counters coupled in series, one of which has n bits.

Claim 11

A device according to claim 7 wherein the means for converting to pulses the signals generated by the combining means includes means for switching the pulses providing said pulses on an addition output or on a subtracting output according to the difference between the frequencies of the signals received is positive or negative, and wherein each computation means comprises two adding-subtracting binary counters, coupled in series, one with n bits for fractional numbers, the other with m bits for whole numbers, a binary register with (m + p) bits an assembly of logic elements comprising a first AND gate and a second AND gate connected to the adding output of the switching means, a third AND gate and a fourth AND gate connected to the subtracting output thereof, a fifth and a sixth AND gate, whose outputs are respectively connected to an adding input and to a subtracting input of the adding-subtracting counter with n bits and a seventh AND gate, said last three AND gates being controlled during the measuring time interval by a signal generated by the synchronizing means, the fifth and sixth AND gates being controlled respectively by the first and the fourth AND gates, through a first OR gate and by the second and third AND gates through a second OR gate, the seventh AND gate being also controlled by the adding-subtracting counter with m bits and having its output connected to register, an eighth and a ninth AND gate the inputs of which are respectively connected to the adding and subtracting outputs of the switching means and controlled by a tenth AND gate opened by the reset of the register, first flip-flop circuit controlled by the eighth and ninth AND gates whose symmetrical outputs trigger, respectively, one the second and fourth AND gates, the other the first and third AND gates, an eleventh AND gate with three inputs whose output is connected to the register and also to a twelfth and a thirteenth AND Gate, one of these two latter AND gates being actuated by one of the outputs of the first flip-flop circuit and the other by the other output of the same flip-flop circuit, said eleventh AND gate being actuated simultaneously by the tenth AND gate, through an inverter, by pulses at the frequency fo generated by the synchronizing means and by the outputs of a second flip-flop circuit, the latter being actuated by the tenth AND gate and by an input connected to the synchronizing means for the emptying of the register after achievement of the computation, a fourteenth AND gate whose output is connected to the register and whose inputs are respectively supplied, one with pulses at frequency fo, the other with releasing pulses emanating from the synchronizing means, a conductor for control of manual reset, connected to the adding-subtracting counter with n bits, a third OR gate actuated either by pulses controlling manual reset or by pulses for automatic reset at the end of each computation cycle, emanating from the synchronizing means and whose output is connected to the adding-subtracting counter with m bits and to register and two output channels, one for adding, the other for subtracting, respectively connected to the outputs of the twelfth and thirteenth gates.

Claim 12

A device according to claim 8 wherein the second and third gates of the synchronizing means are controlled through two gates with several inputs connected to several different points of the circuits of the device.

Claim 13

A device according to claim 7 wherein the synchronizing means comprise an oscillator generating oscillations at frequency 2nfo, a first counter means connected to the oscillator, providing at a first output a signal at a frequency fo and at a second output a signal at frequency lower than that of the oscillation generated by the oscillator, a second counter means connected to the second output of the first counter means through a first AND gate actuated at a starting time by a releasing pulse said second counter means supplying, at a first preselected output, pulses indicating the end of the transmission of the intermittent acoustic signals and at a second output a signal at a frequency lower than that of the signal received from the first counter means, providing at one output, pulses indicating the beginning of the transmission of intermittent signals, a second and a third AND gate receiving from the first counter means a signal at frequency fo, the first one controlled through at least one signal at a frequency equal to the difference between the frequency of the waves received along the reference axis and that of the waves received along a second axis, the second one through at least one signal at a frequency equal to the difference between the frequency of the waves received along the reference axis and that of the waves received along a third axis, the outputs of which directly provide pulses indicating the beginning of the operation of counting the difference betwen the accrued numbers of cycles and the reset of the counters of the computing means, said outputs being connected, the first to the input of a fourth means, the second to the input of a fifth counter means, the fourth and the fifth counter means each having a first preselected output producing pulses indicating the end of said counting operation, a second preselected output, producing pulses indicating the end of a computation period, a first flip-flop circuit connected to the input and the first preselected output of the fourth counter means, a second flip-flop circuit connected to the input and to the first preselected output of the fifth counter means, said flip-flop circuits generating at their outputs pulses defining the measuring time interval.

Claim 14

A device acccording to claim 5 wherein the transmission means and the converting means for the waves along each axis comprise a transmitting and receiving transducer and the amplification mEans comprise circuits isolating the amplification means during the transmission of acoustic waves.

Claim 15

A device according to claim 11 wherein each isolating circuit comprises a transformer whose primary is connected to said conversion means and whose secondary is connected to a voltage divider formed of a resistor connected to two diodes mounted in parallel and in opposite directions with respect to each other, whose dynamic resistances in the forward and reverse directions are respectively much lower and much higher than that of resistor, said diodes being connected to polarizing means in the forward direction during the transmission time interval of the intermittent signals and in the reverse direction during said time interval.

Claim 16

A device according to claim 7 wherein the combining means comprise a first frequency converter for mixing the signal at the reference frequency with a signal at the transmitted frequency produced by the synchronizing means, second and third frequency converters for mixing the signal issued from the first converter respectively with the signal received along a second axis and with the same signal phase shifted by 90*, fourth and fifth converters for mixing the signal issued from the first converter respectively with the signal received along a third axis and with the same signal phase shifted by 90*, four frequency multipliers for multiplying the frequencies of the signals issued from the second through fifth converters by 2n and four frequency converters for mixing the signals issued from the multipliers respectively with a signal whose frequency is that of the transmitted frequency multiplied by 2n.

Claim 17

A device according to claim 13 wherein the frequency multiplier by 2n comprises n multiplying units in series, each of which includes two parallel chains connected to the same input, one of them comprising a first peak limiting operational amplifier with two oppositely phased outputs, the other chain comprising a second integrating and peak limiting operational amplifier with two oppositely phased outputs, four differentiating circuits for converting to pulses the peak limited signals, each of them being connected to one of the four outputs of the two amplifiers, four diodes each mounted downstream from one of the differentiating circuits with respect to the current direction, a third operational amplifier means the input of which is connected to the outputs of said four diodes, and a flip-flop circuit connected to the output of the third amplifier, producing a signal at twice the frequency of the input signal.