Patent US3753235A successfully refreshed from Google Patents.
US3753235A
Expired / Lapsed
US
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Monolithic memory module redundancy scheme using prewired substrates
Assignee: International Business Machines Corp
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Filing: 1971-08-18
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Granted: 1973-08-14
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Expires: 1991-08-18
Abstract
Abstract A monolithic memory module for memory systems capable of utilizing both good chips and partially defective chips. Each chip is provided with an extra bit line of storage cells that can be substituted for failing cells and a comparator circuit having pads that can be contacted externally by pre-wired substrates. The pre-wired substrates are designed in different combinations to contact selected numbers of the pads and thus act as constant output read only memories to the chips mounted thereon. That is, each substrate contains connecting wiring for selectively contacting the pads of the comparator circuit either to identify the defective line and substitute for it the redundant line or to disable the redundant line when its use is unnecessary.
Inventors
- 👤 J Daughton
- 👤 J Tomczak
- 👤 F Wiedman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:56
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
172 words
Memory storage system comprising a main memory means for storing data in storage cells, wherein at least one of said storage cells is defective, a substrate, a semiconductor chip, containing thereon said main memory means, a decoder circuit coupled to said main memory means, alternate data storage means, and a comparator circuit, mounted on said substrate, and memory address register means for applying addressing signals to said comparator circuit and to said decoder circuit, said addressing signals containing predetermined signals indicative of the location of said defective cell. said substrate including conductive means for setting said comparator circuit so that said comparator circuit applies a pulse to the decoder circuit and the alternate data storage means only when said predetermined signals Of said addressing signals, indicative of the location of said defective cell, are applied to said comparator, said decoder circuit having inhibit means responsive to said pulse to prevent said decoder circuit from applying an output pulse to said main memory means when said predetermined signals are applied to said comparator.
Claim 2
Dependent Claim
172 words
Memory storage system comprising a main memory means for storing data in storage cells, wherein at least one of said storage cells is defective, a substrate, a semiconductor chip, containing thereon said main memory means, a decoder circuit coupled to said main memory means, alternate data storage means, and a comparator circuit, mounted on said substrate, and memory address register means for applying addressing signals to said comparator circuit and to said decoder circuit, said addressing signals containing predetermined signals indicative of the location of said defective cell. said substrate including conductive means for setting said comparator circuit so that said comparator circuit applies a pulse to the decoder circuit and the alternate data storage means only when said predetermined signals Of said addressing signals, indicative of the location of said defective cell, are applied to said comparator, said decoder circuit having inhibit means responsive to said pulse to prevent said decoder circuit from applying an output pulse to said main memory means when said predetermined signals are applied to said comparator.
Claim 3
Dependent Claim
26 words
The memory system of claim 1 wherein said comparator circuit comprises a series of exclusive OR circuits, each exclusive OR circuit having an externally addressable pad.
Claim 4
Dependent Claim
39 words
The memory system of claim 2, wherein said exclusive OR circuits further have a common output and said common output has an externally addressable pad thereon, and said conductive means for setting is a ground line on said substrate.
Claim 5
Dependent Claim
36 words
The memory system of claim 2 wherein said conductive means for setting is a ground line on said substrate and is connected to the externally addressable pad of at least one of said exclusive OR circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |