Abstract A shift register having a plurality of bits each formed by a pair of serially interconnected synchronous inverter stages operated by nonconcurrent clock pulses. Each inverter has an MOS transistor driver, a capacitive load, and a bilateral MOS transistor output. The shift register is in integrated circuit form on the (110) crystallographic plane with the current flow in all transistors in a direction normal to the (110) crystallographic plane. The logic input is the gate of the MOS transistor driver. The clock pulses are sequentially applied to the two inverter stages so that the logic number is shifted through the bit in two steps. Each clock pulse is applied across the load and driver and also is applied to the gate of the output transistor of the respective stage. ''''Fill,'''' ''''Clear,'''' and ''''Recirculate'''' modes are provided by NAND and NOR logic gates formed in the first bit by connecting two or more MOS transistor drivers for the inverter stages in series or in parallel, respectively. The last stage of the last bit is a unique high speed D.C. buffer capable of driving a highly capacitive circuit external to the shift register at high speed.
A synchronous logic integrated circuit inverter comprising: a driver MOS transistor and a load capacitance connected in series across a pulsed voltage source, the gate of the driver MOS transistor being the logic input of the inverter, and an output MOS transistor connecting the junction between the driver MOS transistor and the load capacitance to the output of the inverter, the gate of the output MOS transistor being connected to the pulsed voltage source wherein said driver and output MOS transistors are disposed on a (110) crystallographic surface of monocrystalline silicon such that current flow through the channels of the MOS transistors is normal to the (110) crystallographic plane.
Claim 2
Dependent Claim
109 words
A synchronous logic integrated circuit inverter comprising: a driver MOS transistor and a load capacitance connected in series across a pulsed voltage source, the gate of the driver MOS transistor being the logic input of the inverter, and an output MOS transistor connecting the junction between the driver MOS transistor and the load capacitance to the output of the inverter, the gate of the output MOS transistor being connected to the pulsed voltage source wherein said driver and output MOS transistors are disposed on a (110) crystallographic surface of monocrystalline silicon such that current flow through the channels of the MOS transistors is normal to the (110) crystallographic plane.
Claim 3
Dependent Claim
85 words
A high speed inverting output buffer comprising a series circuit comprising an MOS transistor and a capacitance interconnected by the base-emitter circuit of a bipolar transistor, the series circuit being connected across a pulsed voltage source, the gate of the MOS transistor being the logic input, the base of the bipolar transistor being connected to the MOS transistor, and the emitter being connected to the capacitance, and the collector being connected to a collector supply voltage, the emitter being the logic output of the buffer.
Claim 4
Dependent Claim
85 words
A high speed inverting output buffer comprising a series circuit comprising an MOS transistor and a capacitance interconnected by the base-emitter circuit of a bipolar transistor, the series circuit being connected across a pulsed voltage source, the gate of the MOS transistor being the logic input, the base of the bipolar transistor being connected to the MOS transistor, and the emitter being connected to the capacitance, and the collector being connected to a collector supply voltage, the emitter being the logic output of the buffer.
Claim 5
Dependent Claim
16 words
The high speed inverting output buffer of claim 2 wherein the buffer is an integrated circuit.
Claim 6
Dependent Claim
31 words
The high speed inverting output buffer of claim 2 wherein said MOS and bipolar transistors are integrated circuit transistors, and said capacitance is a discrete capacitor external to the integrated circuit.