High speed, low power, dynamic shift register with synchronous logic gates

Abstract

Abstract A shift register having a plurality of bits each formed by a pair of serially interconnected synchronous inverter stages operated by nonconcurrent clock pulses. Each inverter has an MOS transistor driver, a capacitive load, and a bilateral MOS transistor output. The shift register is in integrated circuit form on the (110) crystallographic plane with the current flow in all transistors in a direction normal to the (110) crystallographic plane. The logic input is the gate of the MOS transistor driver. The clock pulses are sequentially applied to the two inverter stages so that the logic number is shifted through the bit in two steps. Each clock pulse is applied across the load and driver and also is applied to the gate of the output transistor of the respective stage. ''''Fill,'''' ''''Clear,'''' and ''''Recirculate'''' modes are provided by NAND and NOR logic gates formed in the first bit by connecting two or more MOS transistor drivers for the inverter stages in series or in parallel, respectively. The last stage of the last bit is a unique high speed D.C. buffer capable of driving a highly capacitive circuit external to the shift register at high speed.

Inventors

• 👤 R Crawford

Bibliographic Details