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US3752913A
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Conditional replenishment video encoder with low-frequency compensation
Assignee: AT&T Inc
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Filing: 1972-06-14
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Granted: 1973-08-14
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Expires: 1992-06-14
Abstract
Abstract Video signal samples for all of the picture elements in a frame interval are stored in a frame memory and each new video signal sample is compared with its corresponding sample from the frame memory in order to develop a frame-to-frame difference signal. A movement detector utilizes the frame-to-frame difference signals to determine when a new video signal sample should be utilized to update the old sample stored in the frame memory and be transmitted to the receiving location. An address word accompanies the transmitted video signal amplitude in order to indicate to the receiver the location of the amplitude within the frame interval. Frame-to-frame differences not indicated as belonging to a moving area are integrated for an entire video line interval. If the integration result exceeds a predetermined threshold, indication of this fact is transmitted to the receiver during the horizontal blanking interval. In addition, a compensation value is developed in response to this indication, and this value is utilized during the next video line interval to modify all of the picture element amplitudes stored in the frame memory for that video line interval. As a result, stored picture element amplitudes are changed en masse for an entire line interval in response to low-frequency changes of the type which occur as a result of changes in light intensity.
Inventors
- 👤 D Connor
- 👤 J Limb
- 👤 K Walsh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:18
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/50; H04N19/503; H04N19/507
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
143 words
A redundancy reduction encoder for use with input samples having frame intervals, said encoder comprising memory means for storing an entire frame interval of samples, means for developing a difference between an input sample and a sample from said memory means, means responsive to said difference developing means for generating a control signal which indicates when said input sample is selected for transmission, means for coupling information related to said input sample to a transmission channel in response to said control signal, wherein the improvement comprises a gating means responsive to said control signal for selectively coupling to its output each difference resulting from an input sample that is not selected, means responsive to the output of said gating means for generating a compensation value, and means responsive to said compensation value for changing the amplitude of samples stored in said memory means.
Claim 2
Dependent Claim
143 words
A redundancy reduction encoder for use with input samples having frame intervals, said encoder comprising memory means for storing an entire frame interval of samples, means for developing a difference between an input sample and a sample from said memory means, means responsive to said difference developing means for generating a control signal which indicates when said input sample is selected for transmission, means for coupling information related to said input sample to a transmission channel in response to said control signal, wherein the improvement comprises a gating means responsive to said control signal for selectively coupling to its output each difference resulting from an input sample that is not selected, means responsive to the output of said gating means for generating a compensation value, and means responsive to said compensation value for changing the amplitude of samples stored in said memory means.
Claim 3
Dependent Claim
48 words
A redundancy reduction encoder as defined in claim 1 wherein said means for generating a compensation value includes means for generating a code word to indicate whether said compensation value should be increased or decreased, and a means responsive to said code word for developing said compensation value.
Claim 4
Dependent Claim
37 words
A redundancy reduction encoder as defined in claim 2 wherein said means for generating a code word includes an integrator means for algebraically summing differences appearing at the output of said gating means for a predetermined interval.
Claim 5
Dependent Claim
31 words
A redundancy reduction encoder as defined in claim 3 wherein said means for generating a code word further includes a threshold detector means coupled to the output of said integrator means.
Claim 6
Dependent Claim
54 words
A redundancy reduction encoder as defined in claim 4 wherein said means for generating a code word further includes means for generating a count of the number of differences at the output of said gating means in said predetermined interval, and means for coupling the count to an input of said threshold detector means.
Claim 7
Dependent Claim
79 words
A redundancy reduction encoder as defined in claim 2 wherein said means responsive to said code word for developing a compensation value includes means for developing a modified code word in response to both said code word and a previously stored modified code word, memory means for storing a modified code word for at least a frame interval, and means for coupling a modified code word from said memory means to said means for developing a modifiEd code word.
Claim 8
Dependent Claim
70 words
A redundancy reduction encoder as defined in claim 6 wherein said means for developing a compensation value further includes a two-input adder means having one input coupled to receive said code word and a second input coupled to receive a modified code word from said memory means for storing a modified code word, and an up-down counter means coupled to respond to a summation developed by said two-input adder circuit.
Claim 9
Dependent Claim
118 words
A redundancy reduction video encoder for use with input video signal samples having frame intervals, said encoder comprising a memory means for storing at least a frame interval of samples, means for developing a difference between an input sample and its corresponding sample from said memory means, means responsive to said difference for generating a control signal to indicate that said input sample has been selected for transmission, gating means responsive to said developed difference and said control signal for selectively coupling to its output developed differences which result from input samples that are not selected, and means responsive to the developed differences at the output of said gating means for modifying samples stored in said memory means.
Claim 10
Dependent Claim
118 words
A redundancy reduction video encoder for use with input video signal samples having frame intervals, said encoder comprising a memory means for storing at least a frame interval of samples, means for developing a difference between an input sample and its corresponding sample from said memory means, means responsive to said difference for generating a control signal to indicate that said input sample has been selected for transmission, gating means responsive to said developed difference and said control signal for selectively coupling to its output developed differences which result from input samples that are not selected, and means responsive to the developed differences at the output of said gating means for modifying samples stored in said memory means.
Claim 11
Dependent Claim
93 words
A redundancy reduction video encoder as defined in claim 8 wherein said means for modifying samples stored in said memory means includes means for generating a compensation value in response to the developed differences at the output of said gating means, a summation means having two inputs and an output, means for coupling one of said two inputs to receive previously stored samples from said memory means, means for coupling said output to said means for developing a difference, and means for coupling the compensation value to the other of said two inputs.
Claim 12
Dependent Claim
47 words
A redundancy reduction encoder as defined in claim 9 wherein said means for generating the compensation value includes means for generating a code word to indicate whether said compensation value should be increased or decreased, and means responsive to said code word for developing said compensation value.
Claim 13
Dependent Claim
38 words
A redundancy reduction encoder as defined in claim 10 wherein said means for generating a code word includes an intergrator means for algebraically summing the developed differences at the output of said gating means for a predetermined interval.
Claim 14
Dependent Claim
35 words
A redundancy reduction encoder as defined in claim 11 wherein said means for generating a code word further includes a threshold detector means coupled to respond to the algebraic summation developed by said integrator means.
Claim 15
Dependent Claim
55 words
A redundancy reduction encoder as defined in claim 12 wherein said means for generating a code word further includes means for generating a count of the number of developed differences at the output of said gating means in said predetermined interval, and means for coupling the count to an input of said threshold detector means.
Claim 16
Dependent Claim
78 words
A redundancy reduction encoder as defined in claim 10 wherein said means responsive to said code word for developing a compensation value includes means for developing a modified code word in response to said code word and a previously stored modified code word, memory means for storing a modified code word for at least a frame interval, and means for coupling a modified code word from said memory means to said means for developing a modified code word.
Claim 17
Dependent Claim
70 words
A redundancy reduction encoder as defined in claim 14 wherein said means for developing a compensation value further includes a two-input adder means having one input coupled to receive said code word and a second input coupled to receive a modified code word from said memory means for storing a modified code word, and an up-down counter means coupled to respond to a summation developed by said two-input adder circuit.
References Cited (Backward Citations)
US3533361A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |