Variable length arithmetic unit

Claim 2

An arithmetic and logic unit for a digital processor having variable length data comprising first and second registers for storing binary coded operands, a parallel binary adder, the contents of the first and second registers being coupled to said adder, a binary carry circuit coupled to the output of the binary adder generating a binary carry signal for each order of the parallel binary output bits of the binary adder, control register means storing information specifying the required data length, means responsive to the contents of the control register means for selectively gating bits out in parallel including the least significant bit of the binary adder output, the number of said bits in parallel corresponding to said specified data length, and means responsive to the contents of the control register means for gating out the binary carry signal corresponding to the highest order of the selected bits.

Claim 3

Apparatus as defined in claim 1 further including means for converting the output of the binary adder from a binary code to a binary coded decimal code, a binary-coded decimal carry circuit coupled to the binary adder for generating a decimal carry signal for each group of four bits of the parallel binary adder output, said control register means storing information specifying whether the contents of the first and second registers are in binary code or binary-coded decimal code, and means responsive to the contents of the control register for selectively coupling the binary output or the binary-coded decimal output to said gating means.

Claim 4

In a digital processor having a common data transfer bus for transferring a predetermined maximum number of bits in parallel, a variable word width arithmetic and logic circuit comprising first and second input registers coupled to the data bus for receiving and storing groups of bits in parallel, the number of significant bits in each register being any number up to said maximum number transferable on the data bus, a parallel binary adder means coupled to the input registers for generating at the output of the adder means the binary coded sum of the contents of the first and second input registers, storing means for storing information as to the number of significant bits starting with the least significant bit position selected to be transferred in parallel from the adder to the bus, gating means coupling the output of the adder means to the transfer bus, said gating means being responsive to the contents of the storing means for gating out bits in parallel to the transfer bus, the number of significant bits starting with the least significant bit position gated out being controlled by the contents of the storing means, and second storing means storing a carry bit, said means being coupled to the binary adder, the binary adder including carry generating means generating a carry output signal for each ordeR of the binary sum, and gating means responsive to the contents of the first-mentioned storing means for selectively gating the carry output signal from the highest order of the specified number of bits in the binary sum to the second storing means.

Claim 5

In a digital processor having a common data transfer bus for transferring a predetermined maximum number of bits in parallel, a variable word width arithmetic and logic circuit comprising first and second input registers coupled to the data bus for receiving and storing groups of bits in parallel, the number of significant bits in each register being any number up to said maximum number transferable on the data bus, a parallel binary adder means coupled to the input registers for generating at the output of the adder means the binary coded sum of the contents of the first and second input registers, storing means for storing information as to the number of significant bits starting with the least significant bit position selected to be transferred in parallel from the adder to the bus, gating means coupling the output of the adder means to the transfer bus, said gating means being responsive to the contents of the storing means for gating out bits in parallel to the transfer bus, the number of significant bits starting with the least significant bit position gated out being controlled by the contents of the storing means, and second storing means storing a carry bit, said means being coupled to the binary adder, the binary adder including carry generating means generating a carry output signal for each ordeR of the binary sum, and gating means responsive to the contents of the first-mentioned storing means for selectively gating the carry output signal from the highest order of the specified number of bits in the binary sum to the second storing means.

Claim 6

Apparatus as defined in claim 3 further including means coupled to the first and second registers for generating in response to the contents of said registers a plurality of outputs with a different logical function on each output, and means for selectively coupling any one of the logical function outputs or the adder output to the transfer bus through said gating means.

Claim 7

Apparatus as defined in claim 3 including means for converting the output of the binary adder from a binary code to a binary coded decimal code, a binary-coded decimal carry circuit coupled to the binary adder for generating a decimal carry signal for each group of four bits of the parallel binary adder output, third storing means storing information specifying whether the contents of the first and second registers are in binary code or binary-coded decimal code, and means responsive to the contents of the third storing means for selectively coupling the binary output or the binary-coded decimal output to said gating means.