US3751597A — Time division multiplex network switching unit

Claim 1

Independent Claim 185 words

In combination, a plurality of time division multiplex signal paths arranged as row circuits of a matrix for receiving time division multiplex signals which include for each row circuit plural time slot Signals in recurrent time frames, a plurality of shift registers each comprising a different column signal path of said matrix and each having a register stage corresponding to each of said row circuits, said shift registers further including different numbers from 1 to n of additional stages, respectively, where n is the number of time slot signals per frame on a row circuit, means for selectively coupling each row circuit to a different shift register in each time slot of a frame and at a common corresponding stage of such registers for such row circuit, which common stage is different for each such row circuit, and means for operating all of said registers in unison whereby bit parallel input signals applied in the same time slot to said row circuits subsequently appear in bit series at the output of the one of said column shift registers which was selected during such time slot.

Claim 2

Dependent Claim 185 words

In combination, a plurality of time division multiplex signal paths arranged as row circuits of a matrix for receiving time division multiplex signals which include for each row circuit plural time slot Signals in recurrent time frames, a plurality of shift registers each comprising a different column signal path of said matrix and each having a register stage corresponding to each of said row circuits, said shift registers further including different numbers from 1 to n of additional stages, respectively, where n is the number of time slot signals per frame on a row circuit, means for selectively coupling each row circuit to a different shift register in each time slot of a frame and at a common corresponding stage of such registers for such row circuit, which common stage is different for each such row circuit, and means for operating all of said registers in unison whereby bit parallel input signals applied in the same time slot to said row circuits subsequently appear in bit series at the output of the one of said column shift registers which was selected during such time slot.

Claim 3

Dependent Claim 79 words

The combination in accordance with claim 1 in which said shift registers are magnetic single-wall domain propagation paths, and said selective coupling means comprise controllable magnetic domain generating means each having a data signal input from a row circuit of said matrix and a data signal output to one of said column shift registers, and an electric circuit control input in common for all of said generators which are coupled to a common one of said column shift registers.

Claim 4

Dependent Claim 94 words

In combination, a plurality of magnetic, single-wall domain, time slot interchangers, a plurality of signal delay means each having a different delay, a plurality of signal converters grouped so that a different group of said converters is associated with each of said interchangers, each of said converters being adapted for receiving an electric signal and converting such signal to a magnetic single-wall domain representation of the same signal, and means for applying the outputs of all converters of a group serially to an input of the associated interchanger through one of said delay means.

Claim 5

Dependent Claim 94 words

In combination, a plurality of magnetic, single-wall domain, time slot interchangers, a plurality of signal delay means each having a different delay, a plurality of signal converters grouped so that a different group of said converters is associated with each of said interchangers, each of said converters being adapted for receiving an electric signal and converting such signal to a magnetic single-wall domain representation of the same signal, and means for applying the outputs of all converters of a group serially to an input of the associated interchanger through one of said delay means.

Claim 6

Dependent Claim 82 words

The combination in accordance with claim 3 in which means are provided for applying electric signals to said converters and include an electric circuit for simultaneously enabling a corresponding one of said converters of each of said time slot interchangers in accordance with the information content of an electric signal on such circuit, and means for recurrently enabling all of said converters of each of said time slot interchangers in a different time slot of a signal frame for each such interchanger.

Claim 7

Dependent Claim 64 words

The combination in accordance with claim 4 in which said recurrent enabling means comprises a ring counter having a plurality of outputs and being connected to be driven at the time slot rate of said electric signals, and means for coupling each of said counter outputs to an enabling input to all of said converters of a different one of said time slot interchangers.

Claim 8

Dependent Claim 93 words

The combination in accordance with claim 5 in which each of said converters comprises a magnetic single-wall domain generator connected to be actuated by a discrete one of said ring counter outputs, a magnetic single-wall domain collapser coupling an output of said generator to a unique input of said delay means for one of said electric signals, and means for connecting said collapser to be energized by such electric signal for allowing coupling to the delay means of such interchanger from said generator for only a predetermined signal state of such electric signal.

Claim 9

Dependent Claim 79 words

The combination in accordance with claim 3 in which each of said time slot interchangers comprises at least one magnetic single-wall domain propagation path, plural gating means distributed along said path for causing domain interaction between a data domain in said path and a control domain, and control memory means for supplying control domains to said gating means for selectively steering data domains through different ones of said gating means out of Said propagation path in different time slots.

Claim 10

Dependent Claim 52 words

The combination in accordance with claim 7 in which each of said control memory loops includes domain collapsing means coupled to a different time slot position in such loop, and means are provided for simultaneously actuating all of said loop domain collapsing means in a selectable time slot of a signal frame.

Claim 11

Dependent Claim 104 words

The combination in accordance with claim 7 in which said control memory means comprises a plurality of domain loop circulating paths, means for coupling an output of each such loop path to a different one of said gating means, a loop path input at a corresponding loop position on each of said loop circulating paths, an address insertion shift register propagation path having sufficient stages to store a number of signal bits equal to the number of bits in a signal frame, and domain transfer means coupled between different time slot domain positions along the last-mentioned shift register and respective control memory loop inputs.

Claim 12

Dependent Claim 45 words

The combination in accordance with claim 9 in which said loop coupling means include signal delay paths of different delay propagation lengths distributed in decreasing delay size for gate means distributed along said shift register path from the input to the output of such path.

Claim 13

Dependent Claim 55 words

The combination in accordance with claim 7 in which said gating means are distributed along said one domain propagation path at signal bit intervals of n bits, and each of said recirculation loops is more than n bits in width in a direction that is parallel to the direction of propagation in said one path.

Claim 14

Dependent Claim 151 words

The combination in accordance with claim 7 in which said control memory means comprises a different recirculation control signal storage loop for storing a control signal pattern for each of said gating means, a plurality of domain propagation paths, each of a different length and coupled between one of said loops and one of said gating means for coupling control domains from such loop to said one domain propagation path for propagation therethrough to an end of the last-mentioned path, and means for applying control signal domains to a selectable one of said loops through different amounts of signal propagation delay, said applying means delay being proportioned for each loop with respect to the coupling path propagation delay for such loop so that the total propagation delay through said applying means and one of said loops to said end of said last-mentioned path is the same for any of said loops.

Claim 15

Dependent Claim 106 words

In combination, a plurality of time slot interchangers, a like plurality of signal propagation delay means each coupled for applying signals to inputs of respective ones of said interchangers, each delay means including a predetermined number of input stages and a different number of additional stages, a plurality of time division multiplex signal paths for receiving time division signals, said signals including on each path plural time slot signals in recurrent time frames, and means for controllably coupling time slot signals from all of said paths to respective input stages of a different one of said delay means in each time slot of a time frame.

Claim 16

Dependent Claim 106 words

In combination, a plurality of time slot interchangers, a like plurality of signal propagation delay means each coupled for applying signals to inputs of respective ones of said interchangers, each delay means including a predetermined number of input stages and a different number of additional stages, a plurality of time division multiplex signal paths for receiving time division signals, said signals including on each path plural time slot signals in recurrent time frames, and means for controllably coupling time slot signals from all of said paths to respective input stages of a different one of said delay means in each time slot of a time frame.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1976-08-06	1977-02-05	1977-08-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1980-08-06	1981-02-05	1981-08-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1984-08-06	1985-02-05	1985-08-07	$7700.00	Window Closed / Lapsed

Time division multiplex network switching unit

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