Zero skew clock distribution system

Claim 5

A synchronizing signal distribution system comprising a plurality of circuits which switch to first and second states in response to input signals above and below a predetermined threshold voltage level respectively, a transmission line having a predetermined signal delay time and characteristic impedance, means coupling each of the circuits to the transmission line, and means including a synchronizing signal source having an impedance matching that of the line to minimize reflections for applying signals, having transitions between voltage levels above and below said threshold level, to the line, the transition times of signal transitions of one polarity being sufficiently long to permit the voltage level at all points along the transmission line to be equal when said threshold level is reached during said transitions of one polarity, whereby all of the circuits respond simultaneously to said transitions of one polarity.

Claim 6

A synchronizing signal distribution system comprising a plurality of circuits which switch to first and second states in response to input signals above and below a predetermined threshold voltage level respectively, a transmission line having a predetermined signal delay time and characteristic impedance, means coupling each of the circuits to the transmission line, and means including a synchronizing signal source having an impedance matching that of the line to minimize reflections for applying signals, having transitions between voltage levels above and below said threshold level, to the line, the transition times of signal transitions of one polarity being sufficiently long to permit the voltage level at all points along the transmission line to be equal when said threshold level is reached during said transitions of one polarity, whereby all of the circuits respond simultaneously to said transitions of one polarity.

Claim 7

A minimum skew clock distribution system comprising a plurality of circuits all of which switch to first and second states in response to input signals above and below a predetermined threshold voltage level respectively, a transmission line having a predetermined signal delay time and characteristic impedance, means coupling the circuits to the line, and means having impedance matching that of the line to minimize reflections for applying signals having transitions between voltage levels above and below said threshold level, to the line, the transition times of the signals being sufficiently long to permit the voltage level at all points along the transmission line to be equal when said threshold level is reached during each transition, whereby all of the circuits respond simultaneously to the input signals to the line.

Claim 8

A minimum skew clock distribution system comprising a plurality of circuits all of which switch to first and second states in response to input signals above and below a predetermined threshold voltage level respectively, a transmission line having a predetermined signal delay time and characteristic impedance, means coupling the circuits to the line, and means having impedance matching that of the line to minimize reflections for applying signals having transitions between voltage levels above and below said threshold level, to the line, the transition times of the signals being sufficiently long to permit the voltage level at all points along the transmission line to be equal when said threshold level is reached during each transition, whereby all of the circuits respond simultaneously to the input signals to the line.

Claim 9

A clock signal distribution system comprising an open ended transmission line with a predetermined time delay T and a selected characteristic impedance, a controlled electronic driver coupled to one end of the line, said driver having an output impedance matching that of the transmission line and applying to the line output signals having a slow transition time Tr relative to the delay time of the line so that signal reflections from the other end of the line appear at thE one end of the line before a predetermined threshold voltage is reached, and a plurality of electronic receiver circuits connected to the line at spaced points between the ends thereof and operated in first and second states in response to driver output signals above and below said predetermined threshold voltage respectively.

Claim 10

A clock signal distribution system comprising an open ended transmission line with a predetermined time delay T and a selected characteristic impedance, a controlled electronic driver coupled to one end of the line, said driver having an output impedance matching that of the transmission line and applying to the line output signals having a slow transition time Tr relative to the delay time of the line so that signal reflections from the other end of the line appear at thE one end of the line before a predetermined threshold voltage is reached, and a plurality of electronic receiver circuits connected to the line at spaced points between the ends thereof and operated in first and second states in response to driver output signals above and below said predetermined threshold voltage respectively.

Claim 11

The combination of claim 5 wherein the rise time Tr is selected according to the equation Tr > or = (Vg/Vt) T where: Vg is the maximum voltage transition of the driver output signal, and Vt is the voltage transition from one level of the driver output signal to said predetermined threshold voltage.

Claim 12

A clock signal distribution system comprising a closed loop transmission line with a characteristic impedance Zo and a time delay Tl for signals propagating around the loop, a controlled electronic driver coupled to the line and having an output impedance substantially equal to one-half Zo, a transmission feed line having a characteristic impedance equal to one-half Zo interposed between and coupling the driver to the line, said driver producing output signals having a slow rise time Tr relative to the delay time Tl so that signals applied by the driver to the transmission line propagate along the loop to cause the line voltage to be substantially equal at all points along the line before the threshold voltage is reached, and a plurality of electronic receiver circuits connected to the closed loop transmission line at spaced points and operated in first and second states in response to driver output signals above and below said predetermined threshold voltage respectively, said circuits being biased to switch between said states when said threshold voltage is crossed, whereby all of the circuits switch with minimum skew.

Claim 13

A clock signal distribution system comprising a closed loop transmission line with a characteristic impedance Zo and a time delay Tl for signals propagating around the loop, a controlled electronic driver coupled to the line and having an output impedance substantially equal to one-half Zo, a transmission feed line having a characteristic impedance equal to one-half Zo interposed between and coupling the driver to the line, said driver producing output signals having a slow rise time Tr relative to the delay time Tl so that signals applied by the driver to the transmission line propagate along the loop to cause the line voltage to be substantially equal at all points along the line before the threshold voltage is reached, and a plurality of electronic receiver circuits connected to the closed loop transmission line at spaced points and operated in first and second states in response to driver output signals above and below said predetermined threshold voltage respectively, said circuits being biased to switch between said states when said threshold voltage is crossed, whereby all of the circuits switch with minimum skew.

Claim 14

The combination of claim 5 wherein the rise time Tr is selected according to the equation Tr > or = Vg/Vt . Tl/2 where: Vg is the maximum voltage transition of the driver output signal, and Vt is the voltage transition from one level of the driver output signal to said predetermined threshold voltage.