Address marker encoder in three frequency recording

Claim 1

A method of generating a marker code signal for use in three frequency recording utilizing a seven bit binary downcounter having three stages, each of said stages comprising a flip-flop having J and K input terminals and Q and Q output terminals, said method comprising the steps of: a. initializing said seven bit binary down counter by resetting all flip flops whereby all Q terminals are set to logical zero and all Q terminals are set to logical one; b. changing the state of each flip flop on successive sequential counts in accordance to the following table I, TABLE I Count Q1 Q2 Q3 A 0 0 1 B 0 1 1 C 1 0 1 D 0 0 1 E 1 1 0 F 0 1 0 G 1 0 0 where Q1, Q2, and Q3 are the Q output terminals of the flipflops in the first, second and third stages respectively and where 0 indicates, a low electric signal on its respective Q terminal and 1 indicates a high electric signal on its respective Q terminal and A, B, C, D, E, F, and G represent count times; c. removing from a predetermined stage of said seven bit binary downcounter a predetermined pattern of bits; d. generating in response to said predetermined pattern of bits a marker code signal for use in three frequency recording.

Claim 2

A method of generating a marker code signal for use in three frequency recording utilizing a seven bit binary downcounter having three stages, each of said stages comprising a flip-flop having J and K input terminals and Q and Q output terminals, said method comprising the steps of: a. initializing said seven bit binary down counter by resetting all flip flops whereby all Q terminals are set to logical zero and all Q terminals are set to logical one; b. changing the state of each flip flop on successive sequential counts in accordance to the following table I, TABLE I Count Q1 Q2 Q3 A 0 0 1 B 0 1 1 C 1 0 1 D 0 0 1 E 1 1 0 F 0 1 0 G 1 0 0 where Q1, Q2, and Q3 are the Q output terminals of the flipflops in the first, second and third stages respectively and where 0 indicates, a low electric signal on its respective Q terminal and 1 indicates a high electric signal on its respective Q terminal and A, B, C, D, E, F, and G represent count times; c. removing from a predetermined stage of said seven bit binary downcounter a predetermined pattern of bits; d. generating in response to said predetermined pattern of bits a marker code signal for use in three frequency recording.

Claim 5

An apparatus for recording binary information in patterns of presences and absences of pulses encoded in 3F code in consecutive positions along A track so that a stream of 3f encoded binary information is preceded by unique marker signals comprising: a. a seven bit binary downcounter having three stages, each stage comprised of JK flip-flops each flip-flop having J and K input terminals and Q and Q output terminals and with the Q output terminal of the first flip-flop coupled to the J input terminal of the second flip-flop, and with the J input terminal of the first flip-flop coupled to the K input terminal of the second flip-flop; b. first, second and third AND gate means each AND gate means having at least two input terminals Alpha and Beta and an output terminal delta , said AND gates means having their delta output terminals logically OR-coupled together and also coupled to the J input terminal of the first flip-flop, said first AND gate means and said second AND gate means having their Alpha input terminals coupled together, said second AND gate means and said third AND gate means having their Beta input terminals coupled together, and with the Beta input terminal of the first AND gate means also coupled to the Alpha input terminal of the third AND gate means; c. fourth and fifth AND gate means, each AND gate means having at least two input terminals Alpha and Beta and an output terminal delta , with the delta output terminal of the fourth AND gate means coupled to the J input terminal of the third flip-flop means and the delta output terminal of the fifth AND gate means coupled to the K input terminal of the third flip-flop means and with the Alpha input terminal of the fourth AND gate means coupled to the Q output terminal of the third flip-flop means, also with the Beta input terminal of the fifth AND gate means coupled to the J input terminal of the second flip-flop means the Q output terminal of the first flip-flop means and also the Beta input terminals of the second and third AND gate means respectively, said fourth AND gate means also having its Beta input terminal coupled with the Alpha input terminal of the fifth AND gate means, said Alpha and Beta input terminals of said fourth and fifth AND gate means also coupled to the Q output terminal of the second flip-flop means, said fourth AND gate means also having a third input terminal gamma said third input terminal coupled to the J input terminals of the second flip-flop means the Q output terminal of the first flip-flop means and the Beta input terminals of said second and third AND gate means respectively; and, d. a marker pulse counter coupled to the second stage of said downcounter.

Claim 6

An apparatus for recording binary information in patterns of presences and absences of pulses encoded in 3F code in consecutive positions along A track so that a stream of 3f encoded binary information is preceded by unique marker signals comprising: a. a seven bit binary downcounter having three stages, each stage comprised of JK flip-flops each flip-flop having J and K input terminals and Q and Q output terminals and with the Q output terminal of the first flip-flop coupled to the J input terminal of the second flip-flop, and with the J input terminal of the first flip-flop coupled to the K input terminal of the second flip-flop; b. first, second and third AND gate means each AND gate means having at least two input terminals Alpha and Beta and an output terminal delta , said AND gates means having their delta output terminals logically OR-coupled together and also coupled to the J input terminal of the first flip-flop, said first AND gate means and said second AND gate means having their Alpha input terminals coupled together, said second AND gate means and said third AND gate means having their Beta input terminals coupled together, and with the Beta input terminal of the first AND gate means also coupled to the Alpha input terminal of the third AND gate means; c. fourth and fifth AND gate means, each AND gate means having at least two input terminals Alpha and Beta and an output terminal delta , with the delta output terminal of the fourth AND gate means coupled to the J input terminal of the third flip-flop means and the delta output terminal of the fifth AND gate means coupled to the K input terminal of the third flip-flop means and with the Alpha input terminal of the fourth AND gate means coupled to the Q output terminal of the third flip-flop means, also with the Beta input terminal of the fifth AND gate means coupled to the J input terminal of the second flip-flop means the Q output terminal of the first flip-flop means and also the Beta input terminals of the second and third AND gate means respectively, said fourth AND gate means also having its Beta input terminal coupled with the Alpha input terminal of the fifth AND gate means, said Alpha and Beta input terminals of said fourth and fifth AND gate means also coupled to the Q output terminal of the second flip-flop means, said fourth AND gate means also having a third input terminal gamma said third input terminal coupled to the J input terminals of the second flip-flop means the Q output terminal of the first flip-flop means and the Beta input terminals of said second and third AND gate means respectively; and, d. a marker pulse counter coupled to the second stage of said downcounter.