← Back to Patent Explorer
US3750042A Expired / Lapsed US ⏱️ 0.0 years remaining

Amplifier of controllable gain

Assignee: General Electric Co
•
Filing: 1972-08-21
•
Granted: 1973-07-31
•
Expires: 1992-08-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A voltage controlled A.C. amplifier is described particularly suited for automatic gain control applications and in particular to automatic color control in a color television receiver. The amplifier is adapted for IC fabrication, with D.C. coupling throughout, having a minimum pin count, and a minimum of outboarded components. While the A.C. signal gain of the amplifier is controllable by voltage adjustment, the D.C. gain is substantially unity. The amplifier takes the form of a modified four-quadrant multiplier with two upper rank differentially connected transistor pairs whose emitters are driven by a lower rank differentially connected transistor pair, the latter preferably flanked by a pair of emitter followers. The input signal is normally applied to the base of one flanking emitter follower through a high pass coupling network. The gain control function is achieved by selective regenerative or degenerative feedback controlled by the interbase potential applied to the upper rank transistor pair. The feedback is applied to the lower rank transistors through a feedback network which is balanced for D.C. but which has a differential affect for A.C. and in particular a low pass coupling characteristic to the lower rank transistor to which the input signal is coupled.

Inventors

  • 👤 W Peil
  • 👤 R Mcfadyen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 06:16
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/70; H04N9/71; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3052

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 300 words
An amplifier of controllable A.C. signal gain comprising: a. a first and a second pair of transistors in an upper rank, the emitters of each transistor pair being joined; one collector of a transistor in each pair being joined and coupled to a source of D.C. bias potential, and the collector of the other transistor in each pair being joined and coupled through a common load impedance to a source of D.C. bias potentials, b. a lower rank transistor pair having its emitters paired and led to a current source for mutually complemented signal coupling, the collector of each lower rank transistor being connected to contRol the emitter current in one upper rank transistor pair; c. means coupling an A.C. input signal to the base of a first lower rank transistor, said coupling means having a high pass characteristic and presenting a complex input impedance to said base, said lower rank transistors forming mutually complemented signals in the emitter current of each upper rank transistor pair, d. means for applying a D.C. interbase control potential to each upper rank transistor pair, balanced at said collector load impedance, for adjusting the relative proportions of said complemented signals in the composite signal in said load, e. means for coupling said composite signal to both bases of said lower rank transistors in a feedback network which is symmetrical from a D.C. standpoint to provide negligible interbase potential and which from an A.C. standpoint is nonsymmetrical at signal frequencies, as a result of imbalance by said complex input impedance, to provide substantial interbase feedback potential, the amount and phase thereof being adjustable by said interbase control potential, and f. output means coupled between like input electrodes of said lower rank transistor pair for deriving an output signal whose amplitude reflects said interbase control potential.
Claim 2
Dependent Claim 300 words
An amplifier of controllable A.C. signal gain comprising: a. a first and a second pair of transistors in an upper rank, the emitters of each transistor pair being joined; one collector of a transistor in each pair being joined and coupled to a source of D.C. bias potential, and the collector of the other transistor in each pair being joined and coupled through a common load impedance to a source of D.C. bias potentials, b. a lower rank transistor pair having its emitters paired and led to a current source for mutually complemented signal coupling, the collector of each lower rank transistor being connected to contRol the emitter current in one upper rank transistor pair; c. means coupling an A.C. input signal to the base of a first lower rank transistor, said coupling means having a high pass characteristic and presenting a complex input impedance to said base, said lower rank transistors forming mutually complemented signals in the emitter current of each upper rank transistor pair, d. means for applying a D.C. interbase control potential to each upper rank transistor pair, balanced at said collector load impedance, for adjusting the relative proportions of said complemented signals in the composite signal in said load, e. means for coupling said composite signal to both bases of said lower rank transistors in a feedback network which is symmetrical from a D.C. standpoint to provide negligible interbase potential and which from an A.C. standpoint is nonsymmetrical at signal frequencies, as a result of imbalance by said complex input impedance, to provide substantial interbase feedback potential, the amount and phase thereof being adjustable by said interbase control potential, and f. output means coupled between like input electrodes of said lower rank transistor pair for deriving an output signal whose amplitude reflects said interbase control potential.
Claim 3
Dependent Claim 42 words
An amplifier as set forth in claim 1 wherein said high pass coupling means comprises a serially connected capacitance (Cs) and resistance coupling said input signal to the base of said first transistor and presenting a low pass characteristic to said feedback.
Claim 4
Dependent Claim 43 words
An amplifier as set forth in claim 2 wherein said feedback network comprises an emitter follower whose base is coupled to said common load impedance and whose emitter is coupled to each lower rank transistor base through a like valued serial feedback resistance.
Claim 5
Dependent Claim 51 words
An amplifier as set forth in claim 3 wherein a pair of emitter followers is provided for coupling the feedback signal available through said serial feedback resistances to the bases of said lower rank transistors, and wherein said output means are coupled between the bases of said lower rank transistor pair.
Claim 6
Dependent Claim 66 words
An amplifier as set forth in claim 4 wherein the forward gain (A(o)) of said amplifier calculated between the base of said first lower rank transistor and the emitter of said emitter follower is less than one (1) plus the ratio of said serial signal resistance (Rs) and the internal source resistance (Ris) to said serial feedback resistance (Rf) Ao < (1 + Rs + Ris/Rf).
Claim 7
Dependent Claim 79 words
An amplifier as set forth in claim 5 wherein the geometric means of the cut off frequency of the amplifier ( omega o) and the cut off frequency of said feedback network ( omega i) approximates the center signal frequency, the cut off frequency of said feedback network being defined as: omega i 1/Cs (Rs + Ris + Rf) to cause the amplifier to have a frequency selective characteristic peaking at said center signal frequency at maximum gain condition.

References Cited (Backward Citations)

US3452289A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-07-30 1977-01-29 1977-07-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-07-30 1981-01-29 1981-07-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-07-30 1985-01-29 1985-07-31 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag