US3750026A
Expired / Lapsed
US
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Intersymbol interference component eliminating system
Assignee: NTT Inc
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Filing: 1972-07-24
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Granted: 1973-07-31
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Expires: 1992-07-24
Abstract
Abstract An intersymbol interference component eliminating system having a demodulator supplied with a carrier wave to demodulate an amplitude modulated digital symbol synchronized with a timing signal, and an intersymbol interference component eliminating circuit including a delay line supplied with a demodulated digital symbol derived from the demodulator, a weighting circuit Aj(j n, -(n- 1), . . . -1, 0, +1, . . . +(n-1) and +n) supplied with an output derived from a terminal Qj of the delay line, a circuit for summing outputs of the weighting circuits and a circuit for generating a weight coefficient control signal Dj based on the output of the summing circuit and the timing signal, the circuit Aj being controlled in its weight coefficient Cj by the signal Dj, in which circuits are provided for generating carrier wave and timing signal phase control signals respectively based on the signals D n, D (n 1), . . . D 1, D 1, . . . D (n 1) and D n, the carrier wave and timing signal phase control signals corresponding to C respectively (k -n, -(n-1), . . . -1, +1, . . . +(n-1) and +n) and Alpha k and Alpha ''k being predetermined weight coefficients corresponding to the coefficient Ck in the case where only the phases of the carrier wave and the timing signal shift by predetermined amounts respectively, and circuits are provided for shifting the phases of the carrier wave and the timing signal based on the carrier wave and timing signal phase control signals respectively.
Inventors
- 👤 K Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:29
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03127; H04L25/03878; H04L25/03885; H04L27/00; H04L27/02; H04L27/06; H04L27/066
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
357 words
An intersymbol interference component eliminating system comprising: i. a demodulator for demodulating an amplitude modulated signal by supplying a carrier wave extracted from the amplitude modulated signal to obtain a demodulated digital signal, the amplitude modulated signal being produced by the amplitude modulation of a carrier wave with a digital signal composed of at least a sequence of timing signals, ii. intersymbol interference component eliminating means including a delay line having a plurality of terminals Q n , Q (n 1), . . . Q 1, Q0, Q 1, . . . Q (n 1) and Q n (n1 and n2 being integers) sequentially led out therefrom and supplied with the demodulated digital signal derived from the demodulator, a plurality of weighting circuits A n , A (n 1), . . . A 1, A0, A 1, . . . A (n 1) and A n supplied with outputs derived from the plurality of terminals Q n, Q (n 1), . . . Q 1, Q0, Q 1, . . . Q (n 1) and Q n of the delay line, summing means for summing outputs derived from the plurality of weighting circuits, and weight coefficient control signal generating means for generating a plurality of weight coefficient control signals D n , D (n 1), . . . D 1, D0, D 1, . . . D (n 1) and D n based on the output of the summing means and the sequence of timing signals, the weighting circuit Aj (j being -n1, -(n1-1), . . . -1, 0, +1, . . . +(n2-1) and +n2) being controlled in its weight coefficient Cj by the weight coefficient control signal Dj, which is characterized by iii. carrier wave phase control signal generating means for generating a carrier wave phase control signal based on the weight coefficient control signals D m , D (m 1), . . . D 1, D 1, . . . D (m 1) and D m , (m1 and m2 being integers, m1 < n1 and m2 < n2) the carrier wave phase control signal corresponding to a correlation value Delta IC represented by
Claim 2
Dependent Claim
357 words
An intersymbol interference component eliminating system comprising: i. a demodulator for demodulating an amplitude modulated signal by supplying a carrier wave extracted from the amplitude modulated signal to obtain a demodulated digital signal, the amplitude modulated signal being produced by the amplitude modulation of a carrier wave with a digital signal composed of at least a sequence of timing signals, ii. intersymbol interference component eliminating means including a delay line having a plurality of terminals Q n , Q (n 1), . . . Q 1, Q0, Q 1, . . . Q (n 1) and Q n (n1 and n2 being integers) sequentially led out therefrom and supplied with the demodulated digital signal derived from the demodulator, a plurality of weighting circuits A n , A (n 1), . . . A 1, A0, A 1, . . . A (n 1) and A n supplied with outputs derived from the plurality of terminals Q n, Q (n 1), . . . Q 1, Q0, Q 1, . . . Q (n 1) and Q n of the delay line, summing means for summing outputs derived from the plurality of weighting circuits, and weight coefficient control signal generating means for generating a plurality of weight coefficient control signals D n , D (n 1), . . . D 1, D0, D 1, . . . D (n 1) and D n based on the output of the summing means and the sequence of timing signals, the weighting circuit Aj (j being -n1, -(n1-1), . . . -1, 0, +1, . . . +(n2-1) and +n2) being controlled in its weight coefficient Cj by the weight coefficient control signal Dj, which is characterized by iii. carrier wave phase control signal generating means for generating a carrier wave phase control signal based on the weight coefficient control signals D m , D (m 1), . . . D 1, D 1, . . . D (m 1) and D m , (m1 and m2 being integers, m1 < n1 and m2 < n2) the carrier wave phase control signal corresponding to a correlation value Delta IC represented by
Claim 3
Dependent Claim
343 words
An intersymbol interference component eliminating system comprising: i. a demodulator for demodulating an amplitude modulated signal by supplying a carrier wave extracted from the amplitude modulated signal to obtain a demodulated digital signal, the amplitude modulated signal being produced by the amplitude modulation of a carrier wave with a digital signal composed of at least a sequence of timing signals, ii. intersymbol interference component eliminating means including a delay line having a plurality of terminals Q n , Q (n 1), . . . Q 1, Q0, Q 1, ... Q (n 1) and Q n (n1 and n2 being integers) sequentially led out therefrom and supplied with the demodulated digital signal derived from the demodulator, a plurality of weighting circuits A n , A (n 1), ...A 1, A0, A 1,...A (n 1) and A n supplied with outputs derived from the Plurality of terminals Q n , Q (n 1), . . . Q 1, Q0, Q 1, . . . Q (n 1) and Q n of the delay line, summing means for summing outputs derived from the plurality of weighting circuits, and weight coefficient control signal generating means for generating a plurality of weight coefficient control signals D n , D (n 1), . . . D 1, D0, D 1, . . . D (n 1) and D n based on the output of the summing means and the sequence of timing signals, the weighting circuit Aj (j being -n1, -(n1-1), . . . -1, 0, +1, . . . +(n2-1) and +n2) being controlled in its weight coefficient Cj by the weight coefficient control signal Dj, which is characterized by iii. timing signal phase control generating means for generating a timing signal phase control signal based on the weight coefficient control signals D m , D (m 1), . . . D 1, D 1, D (m 1) and D m (m1''and m2'' being integers, m1'' < n1 and m2'' < n2), the timing signal phase control signal corresponding to a correlation value Delta IT represented by
Claim 4
Dependent Claim
343 words
An intersymbol interference component eliminating system comprising: i. a demodulator for demodulating an amplitude modulated signal by supplying a carrier wave extracted from the amplitude modulated signal to obtain a demodulated digital signal, the amplitude modulated signal being produced by the amplitude modulation of a carrier wave with a digital signal composed of at least a sequence of timing signals, ii. intersymbol interference component eliminating means including a delay line having a plurality of terminals Q n , Q (n 1), . . . Q 1, Q0, Q 1, ... Q (n 1) and Q n (n1 and n2 being integers) sequentially led out therefrom and supplied with the demodulated digital signal derived from the demodulator, a plurality of weighting circuits A n , A (n 1), ...A 1, A0, A 1,...A (n 1) and A n supplied with outputs derived from the Plurality of terminals Q n , Q (n 1), . . . Q 1, Q0, Q 1, . . . Q (n 1) and Q n of the delay line, summing means for summing outputs derived from the plurality of weighting circuits, and weight coefficient control signal generating means for generating a plurality of weight coefficient control signals D n , D (n 1), . . . D 1, D0, D 1, . . . D (n 1) and D n based on the output of the summing means and the sequence of timing signals, the weighting circuit Aj (j being -n1, -(n1-1), . . . -1, 0, +1, . . . +(n2-1) and +n2) being controlled in its weight coefficient Cj by the weight coefficient control signal Dj, which is characterized by iii. timing signal phase control generating means for generating a timing signal phase control signal based on the weight coefficient control signals D m , D (m 1), . . . D 1, D 1, D (m 1) and D m (m1''and m2'' being integers, m1'' < n1 and m2'' < n2), the timing signal phase control signal corresponding to a correlation value Delta IT represented by
Claim 5
Dependent Claim
84 words
An intersymbol interference component eliminating system according to claim 1, further comprising v. timing signal phase control signal generating means for generating a timing signal phase control signal based on the weight coefficient control signals D m , D (m 1), . . . D 1, D 1, . . . D (m 1) and D m (m1'' and m2'' being integers, m1'' < n1 and m2'' < n2), the timing signal phase control signal corresponding to a correlation value Delta IT represented by
Claim 6
Dependent Claim
122 words
An intersymbol interference component eliminating system according to claim 1, wherein the amplitude modulated signal is produced by the amplitude modulation of the carrier wave with a composite digital signal composed of the sequence of digital symbols and the sequence of timing signals and which further includes v. timiNg signal extracting means for extracting the sequence of timing signals from the demodulated composite digital signal derived from the demodulator, and vi. timing signal eliminating means for eliminating the sequence of timing signals from the demodulated composite digital signal derived from the demodulator by supplying the sequence of timing signals derived from the timing signal eliminating means and supplying the sequence of resulting demodulated digital symbols to the intersymbol interference component eliminating means.
References Cited (Backward Citations)
US3617635A
Cited
US3659229A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |