US3617635A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing recovery system in which an equalizer{40 s sampling time is set in response to the difference between the actual mean square error and a predetermined acceptable error
Assignee: AT&T Inc
•
Filing: 1970-05-15
•
Granted: 1971-11-02
•
Expires: 1990-05-15
Abstract
Abstract A system is disclosed in which an error signal used for adjusting tap weights in a time domain equalizer is integrated in an up-down counter over one-half of an interval. At the end of the first one-half of the interval, the count in the counter is decreased by a predetermined amount proportional to a minimum acceptable error level. The count in the counter is then reduced at a predetermined rate until the count in the counter is zero. During the time the count is being reduced at the predetermined rate, the sampling time of a signal applied to the equalizer is phase shifted in a direction determined by the difference between the integrated error in the present and preceding intervals.
Inventors
- 👤 Donald Hirsch
- 👤 Howard Clarence Meadors Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:49
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0062; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03038
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
145 words
In combination: a time domain equalizer for equalizing a sampled data signal having a predetermined sampling rate to provide an equalized data signal and an error signal indicative of the difference between said equalized data signal and an ideal data signal; means responsive to a received data signal, having a data rate related to said predetermined sampling rate, rendered effective by a sampling pulse for providing said sampled data signal; means responsive to said error signal for providing an average error signal; means for providing a predetermined minimum acceptable error reference signal means responsive to the difference between said average error signal and said predetermined minimum acceptable error reference signal reference signal for providing a control signal, and means responsive to said control signal for providing said sampling signal at a phase with respect to said received data signal as determined by said control signal.
Claim 2
Dependent Claim
145 words
In combination: a time domain equalizer for equalizing a sampled data signal having a predetermined sampling rate to provide an equalized data signal and an error signal indicative of the difference between said equalized data signal and an ideal data signal; means responsive to a received data signal, having a data rate related to said predetermined sampling rate, rendered effective by a sampling pulse for providing said sampled data signal; means responsive to said error signal for providing an average error signal; means for providing a predetermined minimum acceptable error reference signal means responsive to the difference between said average error signal and said predetermined minimum acceptable error reference signal reference signal for providing a control signal, and means responsive to said control signal for providing said sampling signal at a phase with respect to said received data signal as determined by said control signal.
Claim 3
Dependent Claim
48 words
The combination as defined in claim 1 in which said means responsive to said error signal is operative during a first interval; said means responsive to said control signal is operative during a second interval; and both of said immediately aforementioned means are inoperative during a third interval.
Claim 4
Dependent Claim
18 words
The combination as defined in claim 2 in which said first intErval is longer than said second interval.
Claim 5
Dependent Claim
20 words
The combination as defined in claim 3 in which said second interval is short with respect to said third interval.
Claim 6
Dependent Claim
20 words
The combination as defined in claim 1 in which said means responsive to said error signal includes an up-down counter.
Claim 7
Dependent Claim
32 words
The combination as defined in claim 5 in which said means responsive to the difference between said average error and reference signals includes a storage register and an algebraic sign sampling circuit.
Claim 8
Dependent Claim
22 words
The combination as defined in claim 6 in which said means responsive to said control signal includes a variable count preset counter.
References Cited (Backward Citations)
US3537038A
Cited
US3544716A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-01 | 1975-05-03 | 1975-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-01 | 1979-05-03 | 1979-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-01 | 1983-05-03 | 1983-11-02 | $7700.00 | Window Closed / Lapsed |