Instantaneous current control for static inverters

Claim 2

In combination with a three phase inverter, said inverter being characterized as comprising a plurality of single phase sub-inverters whose outputs are combined to form the total inverter output wherein the harmonic content of the total inverter output is lower than the output of one single phase subinverter, the improvement which comprises: means responsive to load faults for limiting instantaneous curren in each of the sub-inverters to a predetermined value during load faults, said means being operative to limit current in the one or more subinverters in which there is an overcurrent resulting from a load fault.

Claim 3

In combination with an inverter of the type comprising a set of at least two single phase sub-inverters whose outputs are combined to form the total inverter output and, in which, the output of each of the sub-inverters is of the same frequency but at a different time phase with respect to each other such that the combined output of the sub-inverters has lower harmonic content than the output of a single sub-inverter, and wherein the voltage regulation means of the inverter causes changes in the output waveform of each subinverter such that the waveforms of the sub-inverters remain substantially identical to each other at all positions of the voltage regulating function, and further wherein, means are provided for producing control signals which control the sub-inverters and the output voltage of each of them, the improvement which comprises: means responsive to load faults for limiting instantaneous current in each of the sub-inverters to a predetermined value during load faults, said means being operative, as required, to limit current in one or more overloaded sub-inverter of the set, said means comprising: a. electric circuit apparatus operatively connected to each sub-inverter for sensing current at each sub-inverter; b. detection means operatively connected to the electric circuit apparatus for detecting when the current magnitude of each sub-inverter is approaching the predetermined value; and c. electric circuit logic means operatively connected to the detection means for modifying the signals controlling the sub-inverters such as to cause the output voltage of the sub-inverters to be changed in a manner tending to reduce any overcurrent in the one or more sub-inverters in which there is an overcurrent resulting from a load fault.

Claim 4

In combination with an inverter of the type comprising a set of at least two single phase sub-inverters whose outputs are combined to form the total inverter output and, in which, the output of each of the sub-inverters is of the same frequency but at a different time phase with respect to each other such that the combined output of the sub-inverters has lower harmonic content than the output of a single sub-inverter, and wherein the voltage regulation means of the inverter causes changes in the output waveform of each subinverter such that the waveforms of the sub-inverters remain substantially identical to each other at all positions of the voltage regulating function, and further wherein, means are provided for producing control signals which control the sub-inverters and the output voltage of each of them, the improvement which comprises: means responsive to load faults for limiting instantaneous current in each of the sub-inverters to a predetermined value during load faults, said means being operative, as required, to limit current in one or more overloaded sub-inverter of the set, said means comprising: a. electric circuit apparatus operatively connected to each sub-inverter for sensing current at each sub-inverter; b. detection means operatively connected to the electric circuit apparatus for detecting when the current magnitude of each sub-inverter is approaching the predetermined value; and c. electric circuit logic means operatively connected to the detection means for modifying the signals controlling the sub-inverters such as to cause the output voltage of the sub-inverters to be changed in a manner tending to reduce any overcurrent in the one or more sub-inverters in which there is an overcurrent resulting from a load fault.

Claim 5

An inverter as recited in claim 2 wherein said electric circuit apparatus comprises current transformer means.

Claim 6

In combination with a three phase inverter whose unfiltered output waveform contains no harmonics lower than the 11th, said inverter being further characterized as comprising at least one three phase transformer having primary and secondary windings, and a set of six single phase subinverters whose outputs are combined to form the total inverter output, the improvement which comprises: means responsive to load faults for limiting instantaneous current in each of the sub-inverters to a predetermined value during load faults, said means being operative to limit current in the one or more subinverters in which there is an overcurrent resulting from a load fault.

Claim 7

In combination with a three phase inverter whose unfiltered output waveform contains no harmonics lower than the 11th, said inverter being further characterized as comprising at least one three phase transformer having primary and secondary windings, and a set of six single phase subinverters whose outputs are combined to form the total inverter output, the improvement which comprises: means responsive to load faults for limiting instantaneous current in each of the sub-inverters to a predetermined value during load faults, said means being operative to limit current in the one or more subinverters in which there is an overcurrent resulting from a load fault.

Claim 8

An inverter as recited in claim 4 wherein said means comprise: a. a plurality of current transformer means, each current transformer being operatively connected to a sub-inverter and each being operatively connected in circuit with the primary winding of the three phase transformer associated with each sub-inverter for sensing current at each sub-inverter in the circuit of the primary winding in each sub-inverter; b. detector means operatively connected to each current transformer means being detecting when the current magnitude of each sub-inverter is approaching the predetermined value; and circuit c. electric circuit logic means operatively connected to the detector means for modifying the output voltage of the sub-inverters in a manner tending to reduce any overcurrent in the one or more sub-inverters in which there is an overcurrent resulting a load fault.

Claim 9

In combination with a solid state inverter utilizing silicon controlled rectifiers and of the type known as the ''''12 step'''' or ''''first harmonic the 11th'''' three phase inverter, the inverter being regulated by vector addition at the three phase transformer primary windings thereof, said inverter being further characterized as comprising a set of six single phase sub-inverters whose outputs are combined to form the total inverter output which appears across the output terminals of the three phase secondary windings of the transformer, the improvement which comprises: a. means responsive to load faults for limiting instantaneous current in the sub-inverters to a predetermined value during a load fault, said means including: i. a plurality of current transformer means, each curent transformer bieng operatively connected to a sub-inverter and each being operatively connected in circuit with the primary winding of the three phase transformer associated with each sub-inverter for sensing current at each sub-inverter in the ciruit of the primary winding in each sub-inverter; ii. detector means operatively connected to each current transformer means for detecting when the current magnitude of each subinverter is approaching the predetermined value; and, iii. electric circuit logic means operatively connected to the detector means for modifying the output voltage of the sub-inverters in a manner which reduces any overcurrent in the one or more sub-inverters in which there is an overcurrent resulting from a load fault.

Claim 10

In combination with a solid state inverter utilizing silicon controlled rectifiers and of the type known as the ''''12 step'''' or ''''first harmonic the 11th'''' three phase inverter, the inverter being regulated by vector addition at the three phase transformer primary windings thereof, said inverter being further characterized as comprising a set of six single phase sub-inverters whose outputs are combined to form the total inverter output which appears across the output terminals of the three phase secondary windings of the transformer, the improvement which comprises: a. means responsive to load faults for limiting instantaneous current in the sub-inverters to a predetermined value during a load fault, said means including: i. a plurality of current transformer means, each curent transformer bieng operatively connected to a sub-inverter and each being operatively connected in circuit with the primary winding of the three phase transformer associated with each sub-inverter for sensing current at each sub-inverter in the ciruit of the primary winding in each sub-inverter; ii. detector means operatively connected to each current transformer means for detecting when the current magnitude of each subinverter is approaching the predetermined value; and, iii. electric circuit logic means operatively connected to the detector means for modifying the output voltage of the sub-inverters in a manner which reduces any overcurrent in the one or more sub-inverters in which there is an overcurrent resulting from a load fault.

Claim 11

In combination with an inverter of the type comprising a set of at least two single phase sub-inverters whose outputs are combined to form the total inverter output and which includes a multiphase transformer having primary and secondary windings and means to limit the instantaneous current of the sub-inverters to a predetermined value in the event of a load fault, which load fault if reflected as an overload in one or more of the sub-inverters, the improvement which comprises: A. means for modifying the operation of one or more of the subinverters in the event of a load fault such as to limit the instantaneous current in the sub-inverters to a predetermined magnitude higher than said predetermined value during an overload in one or more of the sub-inverters, operation of such current control during a given half cycle not changing the operation of the inverter in the subsequent half cycles except as required by overcurrent conditions in said subsequent half cycles, said means including a plurality of current sensing means, each current sensing means being operatively connected to a sub-inverter and each being operatively connected in circuit with the primary winding of the multiphase transformer associated with each sub-inverter for sensing current at each sub-inverter in the circuit of the primary winding in each sub-inverter, the arrangement being such that said means is not directly sensitive to total inverter output current and the total inverter output current may be safely considerably larger than said predetermined value than if the current sensing means were located in circuit with the secondary winding of the multiphase transformer associated with each subinverter and the means to limit the instantaneous current to a predetermined value was set to limit the instantaneous current in the most overloaded subinverter.

Claim 12

In combination with an inverter of the type comprising a set of at least two single phase sub-inverters whose outputs are combined to form the total inverter output and which includes a multiphase transformer having primary and secondary windings and means to limit the instantaneous current of the sub-inverters to a predetermined value in the event of a load fault, which load fault if reflected as an overload in one or more of the sub-inverters, the improvement which comprises: A. means for modifying the operation of one or more of the subinverters in the event of a load fault such as to limit the instantaneous current in the sub-inverters to a predetermined magnitude higher than said predetermined value during an overload in one or more of the sub-inverters, operation of such current control during a given half cycle not changing the operation of the inverter in the subsequent half cycles except as required by overcurrent conditions in said subsequent half cycles, said means including a plurality of current sensing means, each current sensing means being operatively connected to a sub-inverter and each being operatively connected in circuit with the primary winding of the multiphase transformer associated with each sub-inverter for sensing current at each sub-inverter in the circuit of the primary winding in each sub-inverter, the arrangement being such that said means is not directly sensitive to total inverter output current and the total inverter output current may be safely considerably larger than said predetermined value than if the current sensing means were located in circuit with the secondary winding of the multiphase transformer associated with each subinverter and the means to limit the instantaneous current to a predetermined value was set to limit the instantaneous current in the most overloaded subinverter.

Claim 13

An inverter as defined in claim 7 wherein said current sensing means comprise current transformer means.

Claim 14

An inverter as defined in claim 8 wherein said means further includes: a. detctor means operatively connected to each current transformer means for detecting when the current magnitude of each sub-inverter is approaching the predetermined magnitude; and, b. logic means operatively connected to the detector means for modifying the output voltage of the sub-inverters in a manner tending to reduce any overcurrent in the one or more sub-inverters in which there is an overcurrent resulting from a load fault.