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Patent US3749831A successfully refreshed from Google Patents.
US3749831A
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Television multiplexing system
Assignee: National Aeronautics and Space Administration
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Filing: 1972-05-05
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Granted: 1973-07-31
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Expires: 1992-05-05
Abstract
Abstract A television multiplexing system which includes a circuit that inserts a digital coded sync signal and a digital code into a video signal for identifying the channel from which the video signal was generated so that a plurality of signals can be sent over a single hard-line. The digital sync signal and the digital coded signals are generated by a single crystal controlled clock so that they are always in synchronism with each other. In demultiplexing the signals so as to feed the video signal to a proper recording channel the sync signals are utilized for shifting the digital coded signals into a shift register and the shift register, in turn, activates a decoder according to the code stored in the shift register for selecting the proper recording disc or receiver for storing the video signal.
Inventors
- 👤 L Simpkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:37
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/20; H04N21/23; H04N21/236; H04N21/40; H04N21/43; H04N21/434; H04N7/00; H04N7/08; H04N7/087; H04N7/088; H04N7/0887; H04N7/24; H04N7/52; H04N7/54
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
229 words
A system for multiplexing video signals with identifying digital signals so as to identify the video channel from which a particular video signal is generated; A. a video source having a plurality of channels containing video signals; B. means provided by said video source for generating a channel signal for identifying each of said channels; C. means provided by said video source for generating a vertical sync signal; D. a multiplexing system including a timing circuit and a coding circuit for said video signals of each of said channels; E. said timing circuit including; 1. means activated by said vertical sync signal for generating code synchronization pulses, and 2. means for generating shifting pulses synchroniZed with said code synchronization pulses, F. said coding circuit including; 1. a code generator for generating a digital code identifying a particular channel, and 2. a shift register coupled to said code generator, G. means for coupling said channel signal to said code generator for causing said digital code to be shifted into said shift register; H. a multiplexing circuit; I. means for supplying said video signals to said multiplexing circuit; and J. means for supplying said code synchronization pulses and said digital code to said multiplexing circuit for insertion in said video signal; whereby said video signals generated by said video source have identifying digital coded signals and code synchronization pulses inserted therein.
Claim 2
Independent Claim
229 words
A system for multiplexing video signals with identifying digital signals so as to identify the video channel from which a particular video signal is generated; A. a video source having a plurality of channels containing video signals; B. means provided by said video source for generating a channel signal for identifying each of said channels; C. means provided by said video source for generating a vertical sync signal; D. a multiplexing system including a timing circuit and a coding circuit for said video signals of each of said channels; E. said timing circuit including; 1. means activated by said vertical sync signal for generating code synchronization pulses, and 2. means for generating shifting pulses synchroniZed with said code synchronization pulses, F. said coding circuit including; 1. a code generator for generating a digital code identifying a particular channel, and 2. a shift register coupled to said code generator, G. means for coupling said channel signal to said code generator for causing said digital code to be shifted into said shift register; H. a multiplexing circuit; I. means for supplying said video signals to said multiplexing circuit; and J. means for supplying said code synchronization pulses and said digital code to said multiplexing circuit for insertion in said video signal; whereby said video signals generated by said video source have identifying digital coded signals and code synchronization pulses inserted therein.
Claim 3
Dependent Claim
16 words
means for generating shifting pulses synchroniZed with said code synchronization pulses, F. said coding circuit including;
Claim 4
Dependent Claim
16 words
means for generating shifting pulses synchroniZed with said code synchronization pulses, F. said coding circuit including;
Claim 5
Dependent Claim
89 words
a shift register coupled to said code generator, G. means for coupling said channel signal to said code generator for causing said digital code to be shifted into said shift register; H. a multiplexing circuit; I. means for supplying said video signals to said multiplexing circuit; and J. means for supplying said code synchronization pulses and said digital code to said multiplexing circuit for insertion in said video signal; whereby said video signals generated by said video source have identifying digital coded signals and code synchronization pulses inserted therein.
Claim 6
Dependent Claim
89 words
a shift register coupled to said code generator, G. means for coupling said channel signal to said code generator for causing said digital code to be shifted into said shift register; H. a multiplexing circuit; I. means for supplying said video signals to said multiplexing circuit; and J. means for supplying said code synchronization pulses and said digital code to said multiplexing circuit for insertion in said video signal; whereby said video signals generated by said video source have identifying digital coded signals and code synchronization pulses inserted therein.
Claim 7
Dependent Claim
109 words
The system as set forth in claim 1, wherein said timing circuit includes: A. a pulse generating clock for generating a first and second chain of pulses with said second chain of pulses having a frequency greater than said first chain of pulses and said first chain of pulses having a frequency equal to the horizontal sync frequency of said video signal; B. means for activating said pulse generating clock with said vertical sync signal; and C. means activated by said first and second chain of pulses for generating said code synchronization pulses for insertion in said video signal after a predetermined number of horizontal sync pulses have elapsed.
Claim 8
Dependent Claim
41 words
The system as set forth in claim 1, wherein said timing circuit includes: A. a control flip-flop; and B. means for shifting said digital code out of said shift register after said synchronization pulses have been inserted in said video signal.
Claim 9
Dependent Claim
81 words
The system as set forth in claim 1, wherein said means for supplying said video signal to said multiplexing circuit includes: A. a video switch having an input and an output; B. means for coupling said video signal to said input of said video switch; C. means for coupling said output of said video switch to said multiplexing circuit, and D. means activated by said channel signal for enabling said video switch for passing said video signal to said multiplexing circuit.
Claim 10
Dependent Claim
128 words
The system set forth in claim 1, further comprising a demultiplexing system which includes: A. means for receiving said video signal with said digital coded signals and code synchronization pulses inserted therein; B. a plurality of recording means for recording said video signal; C. a shift register; D. means for removing said digital coded signals from said received video signal; E. means for removing said code synchronization pulses from said received video signal and utilizing said code synchronization pulses for shifting said digital coded signals into said shift register, and F. a decoder coupled between said shift register and said plurality of recording means for causing said received video signal to be recorded on a particular recording means determined by the digital coded signals in said shift register.
Claim 11
Dependent Claim
36 words
The system set forth in claim 5 wherein: A. said plurality of recording means are disc recorders, one of said disc recorders being assigned to record video signals from a respective channel of said video source.
References Cited (Backward Citations)
US3647949A
Cited
US3582542A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |