Patent US3748653A successfully refreshed from Google Patents.
US3748653A
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US
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Microprogram memory for electronic computers
Assignee: Bull SAS
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Filing: 1971-10-08
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Granted: 1973-07-24
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Expires: 1991-10-08
Abstract
Abstract A microprogram store having an updating store for holding substitute information elements for use with a fixed microprogram store of an electronic computer, such substitute information elements being replacements for corresponding erroneous or missing information elements in the fixed store, wherein the updating store is an erasable store operated in parallel with the fixed store and supplying an information element held therein whenever an information element in the fixed store is addressed and a corresponding corrected information element is found in the erasable store.
Inventors
- 👤 G Debruyne
- 👤 J Bienvenu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:23
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
435 words
A microprogram memory for an electronic computer having a fixed memory programmed during the fabrication thereof, comprising: an updating erasable memory coupled to operate in parallel with said fixed memory, memory coupled to operate in parallel with said fixed memory, said erasable memory being adapted to hold corrected information elements corresponding to erroneous information elements in said fixed memory, and an information selection device connected to the output terminals of both said erasable memory and said fixed memory for enabling transmission of only correct information elements, wherein a correct information element is provided by said selection device either directly from said fixed memory or from said erasable memory as a substitute for an erroneous information element held in said fixed memory, wherein said selection device is a switch having two channels, the first of said channels being coupled to the output terminal of said fixed memory and the second of said channels being coupled to the output terminal of said erasable memory, said first channel being normally enabled for transmission and said second channel being normally disabled when the information element provided by said fixed memory is correct, whereas said second channel is enabled for transmission and said first channel is disabled when the information element provided by said fixed memory is erroneous and must be replaced by an information element from said erasable memory, wherein said switch is controlled by an electrical control signal supplied by said erasable memory, wherein said erasable memory comprises an associative memory holding the addresses of information elements in said fixed memory to which a correction must be applied and a read/write memory holding the corrected information elements, said associative memory and said read/write memory being coupled in isomorphic manner, whereby one address in said associative memory corresponds to one information element in said read/write memory, and wherein said associative memory furnishes said control signal to said switch when a match is found between the address of the desired information element and one of the addresses held in said associative memory and controls said read/write memory to deliver to said switch the information element held in said read/write memory corresponding to said one address, wherein said switch comprises a pair of two-input ANDgates, an inverter and a two-input OR-gate, the first of said AND-gates having the input terminals thereof respectively connected to said read/write memory and said associative memory, the second of said AND-gates having the input terminals thereof respectively connected to said fixed memory and, through said inverter, to said associative memory, the output terminals of said two AND-gates being connected to respective input terminals of said OR-gate.
Claim 2
Dependent Claim
435 words
A microprogram memory for an electronic computer having a fixed memory programmed during the fabrication thereof, comprising: an updating erasable memory coupled to operate in parallel with said fixed memory, memory coupled to operate in parallel with said fixed memory, said erasable memory being adapted to hold corrected information elements corresponding to erroneous information elements in said fixed memory, and an information selection device connected to the output terminals of both said erasable memory and said fixed memory for enabling transmission of only correct information elements, wherein a correct information element is provided by said selection device either directly from said fixed memory or from said erasable memory as a substitute for an erroneous information element held in said fixed memory, wherein said selection device is a switch having two channels, the first of said channels being coupled to the output terminal of said fixed memory and the second of said channels being coupled to the output terminal of said erasable memory, said first channel being normally enabled for transmission and said second channel being normally disabled when the information element provided by said fixed memory is correct, whereas said second channel is enabled for transmission and said first channel is disabled when the information element provided by said fixed memory is erroneous and must be replaced by an information element from said erasable memory, wherein said switch is controlled by an electrical control signal supplied by said erasable memory, wherein said erasable memory comprises an associative memory holding the addresses of information elements in said fixed memory to which a correction must be applied and a read/write memory holding the corrected information elements, said associative memory and said read/write memory being coupled in isomorphic manner, whereby one address in said associative memory corresponds to one information element in said read/write memory, and wherein said associative memory furnishes said control signal to said switch when a match is found between the address of the desired information element and one of the addresses held in said associative memory and controls said read/write memory to deliver to said switch the information element held in said read/write memory corresponding to said one address, wherein said switch comprises a pair of two-input ANDgates, an inverter and a two-input OR-gate, the first of said AND-gates having the input terminals thereof respectively connected to said read/write memory and said associative memory, the second of said AND-gates having the input terminals thereof respectively connected to said fixed memory and, through said inverter, to said associative memory, the output terminals of said two AND-gates being connected to respective input terminals of said OR-gate.
Claim 3
Dependent Claim
49 words
The microprogram memory of claim 1, coupled for transmitting information elements to a processor and further comprising an interrogation address register coupled to provide an address to both said fixed memory and said associative memory and means for transferring the information element transmitted by said switch to said processor.
Claim 4
Dependent Claim
39 words
a further memory having a plurality of memory positions each including correct information for replacing information designaTed for said faulty memory elements, wherein said further memory has the same addresses as corresponding locations of said plurality of locations, and
Claim 5
Dependent Claim
39 words
a further memory having a plurality of memory positions each including correct information for replacing information designaTed for said faulty memory elements, wherein said further memory has the same addresses as corresponding locations of said plurality of locations, and
Claim 6
Dependent Claim
131 words
means for coupling said further memory with said plurality of locations so that said memory positions of said further memory are accessed when said plurality of locations are addressed; C. means for simultaneously addressing said main memory and said plurality of locations; D. means for generating a control signal when the address provided by said means for addressing compares to one of said addresses of said plurality of locations; and E. switch means coupled to receive information from said main memory and said further memory, said switch means including an output terminal, said switch means normally enabled to transfer said information from said main memory to said output terminal and said switch means responsive to said control signal for transferring only the information from said further memory to said output terminal.
Claim 7
Dependent Claim
131 words
means for coupling said further memory with said plurality of locations so that said memory positions of said further memory are accessed when said plurality of locations are addressed; C. means for simultaneously addressing said main memory and said plurality of locations; D. means for generating a control signal when the address provided by said means for addressing compares to one of said addresses of said plurality of locations; and E. switch means coupled to receive information from said main memory and said further memory, said switch means including an output terminal, said switch means normally enabled to transfer said information from said main memory to said output terminal and said switch means responsive to said control signal for transferring only the information from said further memory to said output terminal.
Claim 8
Dependent Claim
415 words
A microprogram memory for an electronic computer having a fixed memory programmed during the fabrication thereof, comprising: an updating erasable memory coupled to operate in parallel with said fixed memory, said erasable memory being adapted to hold corrected information elements corresponding to erroneous information elements in said fixed memory, and an information selection device connected to the output terminals of both said erasable memory and said fixed memory for enabling transmission of only correct information elements, wherein a correct information element is provided by said selection device either directly from said fixed memory or from said erasable memory as a substitute for an erroneous information element held in said fixed memory, wherein said selection device is a switch having two channels, the first of said channels being coupled to the output terminal of said fixed memory and the second of said channels being coupled to the output terminal of said erasable memory, said first channel being normally enabled for transmission and said second channel being normally disabled when the information element provided by said fixed memory is correct, whereas said second channel is enabled for transmission and said first channel is disabled when the information element provided by said fixed memory is erroneous and must be replaced by an information element from said erasable memory, wherein said switch is controlled by an electrical control signal supplied by said erasable memory, wherein said erasable memory comprises an associative memory holding the addresses of information elements in said fixed memory to which a correction must be applied and a read/write memory holding the corrected information elements, said associative memory and said read/write memory being coupled in isomorphic manner, whereby one address in said associative memory corresponds to one information element in said read/write memory, and wherein said associative memory furnishes said control signal to said switch when a match is found between the address of the desired information element and one of the addresses held in said associative memory and controls said read/write memory to deliver to said switch the information element held in said read/write memory corresponding to said one address,wherein said switch comprises first and second gate means, said first gate means having the input terminals thereof respectively connected to said read/write memory and said associative memory, said second gate means having the input terminals thereof respectively connected to said fixed memory and coupled to said associative memory, the output terminals of said first and second gate means coupled to provide said correct information elements.
Claim 9
Dependent Claim
415 words
A microprogram memory for an electronic computer having a fixed memory programmed during the fabrication thereof, comprising: an updating erasable memory coupled to operate in parallel with said fixed memory, said erasable memory being adapted to hold corrected information elements corresponding to erroneous information elements in said fixed memory, and an information selection device connected to the output terminals of both said erasable memory and said fixed memory for enabling transmission of only correct information elements, wherein a correct information element is provided by said selection device either directly from said fixed memory or from said erasable memory as a substitute for an erroneous information element held in said fixed memory, wherein said selection device is a switch having two channels, the first of said channels being coupled to the output terminal of said fixed memory and the second of said channels being coupled to the output terminal of said erasable memory, said first channel being normally enabled for transmission and said second channel being normally disabled when the information element provided by said fixed memory is correct, whereas said second channel is enabled for transmission and said first channel is disabled when the information element provided by said fixed memory is erroneous and must be replaced by an information element from said erasable memory, wherein said switch is controlled by an electrical control signal supplied by said erasable memory, wherein said erasable memory comprises an associative memory holding the addresses of information elements in said fixed memory to which a correction must be applied and a read/write memory holding the corrected information elements, said associative memory and said read/write memory being coupled in isomorphic manner, whereby one address in said associative memory corresponds to one information element in said read/write memory, and wherein said associative memory furnishes said control signal to said switch when a match is found between the address of the desired information element and one of the addresses held in said associative memory and controls said read/write memory to deliver to said switch the information element held in said read/write memory corresponding to said one address,wherein said switch comprises first and second gate means, said first gate means having the input terminals thereof respectively connected to said read/write memory and said associative memory, said second gate means having the input terminals thereof respectively connected to said fixed memory and coupled to said associative memory, the output terminals of said first and second gate means coupled to provide said correct information elements.
Claim 10
Dependent Claim
27 words
The memory of claim 3 further comprising inverter means coupled in the coupling between said respective input terminal of said second gate means and said associative memory.
Claim 11
Dependent Claim
43 words
The memory of claim 4 further comprising third gate means having the input terminals thereof respectively coupled to said output terminals of said first and second gate means and wherein the output terminal of said third gate means provides said correct information elements.
Claim 12
Dependent Claim
27 words
The memory of claim 5 wherein said first and second gate means each provide an AND function and wherein said third gate means provides an OR function.
Claim 13
Dependent Claim
18 words
A memory system comprising: A. a main memory having some faulty memory elements; B. a correction memory comprising
Claim 14
Dependent Claim
18 words
A memory system comprising: A. a main memory having some faulty memory elements; B. a correction memory comprising
Claim 15
Dependent Claim
62 words
A system as in claim 7 wherein said switch means comprises: A. first gate means coupled to transfer information from said further memory to said output terminal in response to said control signal; and B. second gate means coupled to transfer information from said main memory to said output terminal when said control signal is not generated by said means for generating.
Claim 16
Dependent Claim
76 words
A system as in claim 7 wherein said switch means comprises: A. first and second two-input AND gate means; B. inverter means; C. means for coupling the inputs of said first gate means respectively to said further memory and to said means for generating said control signal; D. means for coupling the inputs of said second gate means respectively to said main memory and, through said inverter means, to said means for generating said control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-23 | 1977-01-22 | 1977-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-23 | 1981-01-22 | 1981-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-23 | 1985-01-22 | 1985-07-24 | $7700.00 | Window Closed / Lapsed |