Patent US3748543A successfully refreshed from Google Patents.
US3748543A
Expired / Lapsed
US
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Hermetically sealed semiconductor package and method of manufacture
Assignee: Motorola Solutions Inc
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Filing: 1971-04-01
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Granted: 1973-07-24
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Expires: 1991-04-01
Abstract
Abstract There is disclosed a hermetically sealed semiconductor package which is physically thin, allowing mounting within apertures formed in printed circuit boards which are stacked one on top of another in a high density configuration. The hermetic seal is made to a planar surface resulting in high reliability devices in which the leads to the interior of the package are made through ''''cross under'''' regions which are provided with planar top surfaces. The ''''cross under'''' region is a region of extremely low resistivity, high temperature material. Because this material is utilized as part of the lead to the device and because the hermetic seal is made on top of the ''''cross under,'''' higher temperatures, which would ordinarily destroy metal leads, can be applied to the sealing material both on top of the ''''cross unders'''' and on top of the substrate for increasing the reliability of the seal. This package replaces the more fragile prior art hermetically sealed devices which include a number of piece parts. A device packaged in the subject manner is also used as a hermetically sealed substitute for beam lead devices, since the subject devices are thin, have a higher reliability than unsealed beam lead devices and are impervious to welding and other contaminants during mounting.
Inventors
- 👤 D Roberson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:00
CPC Classifications
H; H10; H10W; H10W76/00; H10W76/60; H10W20/00; H10W20/20; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
391 words
A minute, hermetically sealed semiconductor package having an active semiconductor device and comprising: a substrate surrounding and abutting against all but one surface of the active semiconductor device and having a planar top surface; a dielectric layer insulating the active semiconductor device from said substrate; ''''cross under'''' regions within said substrate, and in spaced adjacency to said active semiconductor device, said ''''cross under'''' regions being of a low resistivity, high melting point material, and having planar top surfaces flush with the planar top surface of said substrate, the planar top surfaces of said ''''cross under'''' regions and said substrate serving to permit hermetic seals overtop thereof; a dielectric layer insulating said ''''cross under'''' regions from said substrate; a passivation layer over the top surfaces of said substrate and said ''''cross under'''' regions, said passivation layer having a planar top surface and said passivation layer having appertures therethrough over preselected elements in said active semiconductor device and over portions of the surfaces of said ''''cross under'''' regions so as to leave other portions of said ''''cross under'''' regions covered by said passivation layer; a layer of conductive material over said passivation layer and patterned so as to connect selected elements in said active device to first sides of selected ''''cross under'''' regions, and so as to form contact pads secured to said substrate and connected to second sides of said ''''cross under'''' regions, said conductive material contacting said active elements and said ''''cross under'''' regions by extending into said apertures, said conductive material being further patterned to expose the passivation layer over said other portions of said ''''cross under'''' regions; a region of sealing material surrounding said active device and forming a continuous path over the planar top surface of said passivation layer, said sealing material crossing said ''''cross under'''' regions over the planar top surface of the passivation layer extending over said other portions; a lid of a material having a similar thermal coefficient of expansion to that of said substrate positioned over said sealing material and enclosing the area circumscribed by said sealing material but leaving portions of said contact pads exposed, said lid being sealed to the planar top surface of said passivation layer and thereby to the top surfaces of said ''''cross under'''' regions and said substrate by the application of heat sufficient to seal said sealing material.
Claim 2
Dependent Claim
391 words
A minute, hermetically sealed semiconductor package having an active semiconductor device and comprising: a substrate surrounding and abutting against all but one surface of the active semiconductor device and having a planar top surface; a dielectric layer insulating the active semiconductor device from said substrate; ''''cross under'''' regions within said substrate, and in spaced adjacency to said active semiconductor device, said ''''cross under'''' regions being of a low resistivity, high melting point material, and having planar top surfaces flush with the planar top surface of said substrate, the planar top surfaces of said ''''cross under'''' regions and said substrate serving to permit hermetic seals overtop thereof; a dielectric layer insulating said ''''cross under'''' regions from said substrate; a passivation layer over the top surfaces of said substrate and said ''''cross under'''' regions, said passivation layer having a planar top surface and said passivation layer having appertures therethrough over preselected elements in said active semiconductor device and over portions of the surfaces of said ''''cross under'''' regions so as to leave other portions of said ''''cross under'''' regions covered by said passivation layer; a layer of conductive material over said passivation layer and patterned so as to connect selected elements in said active device to first sides of selected ''''cross under'''' regions, and so as to form contact pads secured to said substrate and connected to second sides of said ''''cross under'''' regions, said conductive material contacting said active elements and said ''''cross under'''' regions by extending into said apertures, said conductive material being further patterned to expose the passivation layer over said other portions of said ''''cross under'''' regions; a region of sealing material surrounding said active device and forming a continuous path over the planar top surface of said passivation layer, said sealing material crossing said ''''cross under'''' regions over the planar top surface of the passivation layer extending over said other portions; a lid of a material having a similar thermal coefficient of expansion to that of said substrate positioned over said sealing material and enclosing the area circumscribed by said sealing material but leaving portions of said contact pads exposed, said lid being sealed to the planar top surface of said passivation layer and thereby to the top surfaces of said ''''cross under'''' regions and said substrate by the application of heat sufficient to seal said sealing material.
Claim 3
Dependent Claim
28 words
The package as recited in claim 1 wherein said substrate is polycrystalline silicon, said lid is monocrystalline silicon and said sealing material is infrared absorbing vanadium rich glass.
Claim 4
Dependent Claim
18 words
The package as recited in claim 2 wherein said vanadium rich glass includes a quantity of ferric oxide.
Claim 5
Dependent Claim
68 words
The package as recited in claim 1 and further including a second passivation layer on top of the layer of conductive material over said first mentioned passivation layer, said second passivation layer being provided with apertures therethrough at said contact pads, and at said other portions of said ''''cross under'''' regions thereby permitting sealing material to project through said second passivation layer to contact said first passivation layer.
Claim 6
Dependent Claim
26 words
The package as recited in claim 1 wherein said low resistivity high melting point material forming said ''''cross under'''' regions is a highly doped semiconductor material.
Claim 7
Dependent Claim
22 words
The package as recited in claim 5 wherein said semiconductor material is silicon having a doping concentration in excess of 1020 atoms/cm3.
Claim 8
Dependent Claim
108 words
The package as recited in claim 1 wherein said ''''cross under'''' regions are formed by etching out regions in a body of said low resistivity material in areas adjacent the position where said low resistivity material is to be located, covering the surface of said body which has been etched with a layer of dielectric material, forming said substrate on top of said dielectric layer and lapping said body down to the portion of said substrate extending into said etched regions such that a channel of said low resistivity material is formed having a top surface flush with that portion of the substrate exposed due to said lapping.
Claim 9
Dependent Claim
16 words
The package as recited in claim 1 wherein said dielectric layers are comprised of silicon dioxide.
Claim 10
Dependent Claim
49 words
The package as recited in claim 1 wherein said ''''cross under'''' regions are of a moderately doped semiconductor material which is further doped by the dopant used in forming the active device in said substrate, said ''''cross under'''' regions being doped simultaneously with the formation of said active device.
Claim 11
Dependent Claim
17 words
The package as recited in claim 1 wherein said sealing material is a low temperature recrystallizing glass.
Claim 12
Dependent Claim
126 words
The package as recited in claim 1 and further including a multilayered circuit board having an aperture therethrough corresponding in size to the outside dimensions of said package, said circuit board having a metal strip therethrough with an end portion extending into said aperture, the end portion of said strip extending into said aperture corresponding in position to the location of a contact pad on said substrate when said package is in place in said circuit board, such that said contact pad may be welded to said portion thereby to connect an element in said active device to said strip whereby the mechanical stability of the package in the circuit board is increased due to the mechanical stability of said substrate and the contact pads thereon.
Claim 13
Independent Claim
261 words
A method of manufacturing a plurality of semiconductor devices including the steps of: providing a body of semiconductive material having a surface which is substantially planar; selectively etching selected areas of said planar surface of said body of semiconductive material; covering the unetched areas of said surface and the etched areas with a dielectric material; forming a substrate on the outwardly facing surface of said dielectric material; removing portions of said body of semiconductive material to leave the unetched regions of said semiconductive body partially embedded in and insulated from said substrate; forming a plurality of active semiconductor components in some of said insulated regions of semiconductive material and a plurality of conductors in other of said regions; placing a passivation layer over selected areas of the outwardly facing surfaces of said active semiconductor components and conductors; forming a layer of conductive material over said passivation layer and over some of the exposed areas of said semiconductor components and conductors to provide electrical interconnection between said semiconductor components and said conductors and to provide contacting pads extending from said conductors; sealing surfaces of lids over said passivation layer such that the edge regions thereof cross over said conductors at areas covered by said passivation layer so that said conductive material does not extend beneath said edge regions of said lids enclosing said active semiconductor components but leaving said contacting pads exposed; and separating selected areas of said substrate which each include an active semiconductor device and at least one of said conductors to thereby provide the plurality of completed semiconductor devices.
Claim 14
Independent Claim
261 words
A method of manufacturing a plurality of semiconductor devices including the steps of: providing a body of semiconductive material having a surface which is substantially planar; selectively etching selected areas of said planar surface of said body of semiconductive material; covering the unetched areas of said surface and the etched areas with a dielectric material; forming a substrate on the outwardly facing surface of said dielectric material; removing portions of said body of semiconductive material to leave the unetched regions of said semiconductive body partially embedded in and insulated from said substrate; forming a plurality of active semiconductor components in some of said insulated regions of semiconductive material and a plurality of conductors in other of said regions; placing a passivation layer over selected areas of the outwardly facing surfaces of said active semiconductor components and conductors; forming a layer of conductive material over said passivation layer and over some of the exposed areas of said semiconductor components and conductors to provide electrical interconnection between said semiconductor components and said conductors and to provide contacting pads extending from said conductors; sealing surfaces of lids over said passivation layer such that the edge regions thereof cross over said conductors at areas covered by said passivation layer so that said conductive material does not extend beneath said edge regions of said lids enclosing said active semiconductor components but leaving said contacting pads exposed; and separating selected areas of said substrate which each include an active semiconductor device and at least one of said conductors to thereby provide the plurality of completed semiconductor devices.
Claim 15
Dependent Claim
23 words
The method as recited in claim 12 wherein said plurality of active semiconductor components and said plurality of conductors are formed by diffusions.
Claim 16
Dependent Claim
131 words
An integrated circuit device comprising: a plurality of semiconductor regions supported by a substrate, selected ones of said regions at the periphery of said substrate having diffused regions comprising conductive cross unders, each of said cross unders having first and second end portions and intermediate portions between said first and second end portions, another of said semiconductor regions in the central portion of said substrate comprising an active semiconductor device having elements; first conductive material connecting said elements of said semiconductor device to said first ends of said cross unders; a lid sealed to said surface of said substrate at intermediate portions of said cross unders and overlying said active semiconductor device; and second conductive material connected to said second portions of said cross unders and located outside of said lid.
Claim 17
Dependent Claim
131 words
An integrated circuit device comprising: a plurality of semiconductor regions supported by a substrate, selected ones of said regions at the periphery of said substrate having diffused regions comprising conductive cross unders, each of said cross unders having first and second end portions and intermediate portions between said first and second end portions, another of said semiconductor regions in the central portion of said substrate comprising an active semiconductor device having elements; first conductive material connecting said elements of said semiconductor device to said first ends of said cross unders; a lid sealed to said surface of said substrate at intermediate portions of said cross unders and overlying said active semiconductor device; and second conductive material connected to said second portions of said cross unders and located outside of said lid.
Claim 18
Dependent Claim
24 words
The integrated circuit of claim 14 wherein said second conductive material forms contact pads located on and connected to the surface of said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-23 | 1977-01-22 | 1977-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-23 | 1981-01-22 | 1981-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-23 | 1985-01-22 | 1985-07-24 | $7700.00 | Window Closed / Lapsed |