Data transmission over pulse code modulation channels

Claim 2

A time division multiplex pulse code modulation intelligence transmission system, each pulse code modulation code combination having n bit positions, where n is an integer greater than three, one bit position being employed for signalling and/or synchronization and (n-1) bit positions being employed for intelligence communication purposes, and capable of transmitting binary data bits by employing said (n-1) bit positions of each time division multiplex channel comprising: a source of binary data bits in a time division multiplex format to be transmitted; first means coupled to said source to store said binary data bits; second means coupled to said source to count the number of said binary data bits stored during the time interval of a time division multiplex channel of said format, said number not exceeding (n-2); and third means coupled to said first and second means to combine said stored binary data bits and a single marker bit, to substitute said stored binary data bits and said marker bit for said (n-1) bit positions of normal intelligence in one of said time division multiplex channels, and to group said stored binary data bits and said marker bit together at one end of said (n-1) bit positions with said marker bit being disposed in the bit position immediately following the last bit of said stored binary data bits so that the location of said marker bit within said (n-1) bit positions defines the number and repetition rate of said stored binary data bits associated therewith.

Claim 3

A system according to claim 1, wherein said first means includes a shift register having (n-2) stages.

Claim 4

A system according to claim 1, wherein said second means includes fourth means coupled to said source to generate clock pulses in synchronism with said binary data bits, each of said clock pulses controlling the insertion of one of said binary data bits into said first means, fifth means coupled to said fourth means to count said clock pulses, and sixth means coupled to said first means and said fifth means to compare the number of said binary data bits stored in said first means with the count of said fifth means and to insert said marker bit in the proper location within said (n-1) bit positions and clear said first means and said fifth means when said number and said count agree.

Claim 5

A time division multiplex pulse code modulation intelligence receiving system, each pulse code modulation code combination having n bit positions, where n is an integer greater than three, one bit position being employed for signalling and/or synchronization and (n-1) bit positions being employed for intelligence communication purposes, wherein at least one set of binary data bits are transmitted from a remote terminal by employing said (n-1) bit positions of at least one of time division multiplex channels, said set of binary data bits including binary data bits whose number does not exceed (n-2) grouped together at one end of said (n-1) bit positions and a single marker bit in the bit position immediately following the last bit of said set of binary data bits, the location of said marker bit within said (n-1) bit positions defining the number and repetition rate of the data bits of said set of binary data bits comprising: a source of said set of binary data bits; first Means coupled to said source to store said set of binary data bits; and second means coupled to said source and said first means to generate clock pulses having a repetition rate as determined by said location of said marker bit within said (n-1) bit positions, said clock pulses controlling the read out of said first means at said repetition rate.

Claim 6

A time division multiplex pulse code modulation intelligence receiving system, each pulse code modulation code combination having n bit positions, where n is an integer greater than three, one bit position being employed for signalling and/or synchronization and (n-1) bit positions being employed for intelligence communication purposes, wherein at least one set of binary data bits are transmitted from a remote terminal by employing said (n-1) bit positions of at least one of time division multiplex channels, said set of binary data bits including binary data bits whose number does not exceed (n-2) grouped together at one end of said (n-1) bit positions and a single marker bit in the bit position immediately following the last bit of said set of binary data bits, the location of said marker bit within said (n-1) bit positions defining the number and repetition rate of the data bits of said set of binary data bits comprising: a source of said set of binary data bits; first Means coupled to said source to store said set of binary data bits; and second means coupled to said source and said first means to generate clock pulses having a repetition rate as determined by said location of said marker bit within said (n-1) bit positions, said clock pulses controlling the read out of said first means at said repetition rate.

Claim 7

A system according to claim 4, wherein said first means includes a shift register having (n-1) stages.

Claim 8

A system according to claim 4, wherein said source includes a plurality of said sets of binary data bits, and said first means includes two shift registers each having (n-1) stages, said shift registers being employed alternately on alternate frames of the time division multiplex signal.

Claim 9

A time division multiplex pulse code modulation intelligence communication system, each pulse code modulation code combination having n bit positions, where n is an integer greater than three, one bit position being employed for signalling and/or synchronizing and (n-1) bit positions being employed for intelligence communication purposes, and capable of enabling the communication with binary data bits by employing said (n-1) bit positions of selected ones of the time division multiplex channels comprising: a source of binary data bits in a time division multiplex format to be transmitted; first means coupled to said source to store said binary data bits; second means coupled to said source to count the number of said binary data bits stored during the time interval of a time division multiplex channel of said format, said number not exceeding (n-2); third means coupled to said first and second means to combine said stored binary data bits and a single marker bit, to substitute said stored binary data bits and said marker bit for said (n-1) bit positions of normal intelligence in one of said time division multiplex channels, and to group said stored binary data bits and said marker bit together at one end of said (n-1) bit positions with said marker bit being disposed in the bit position immediately following the last bit of said stored binary data bits so that the location of said marker bit within said (n-1) bit positions defines the number and repetition rate of said stored binary data bits associated therewith; fourth means coupled to said third means to transmit a combination of said one bit position, said stored binary data bits and said marker bit; fifth means coupled to said fourth means to receive said transmitted combination; sixth means coupled to said fifth means to store said marker bit and said binary data bits; and seventh means coupled to said fifth and sixth means to generate clock pulses having a repetition rate as determined by said location of said marker bit within said (n-1) bit positions, said clock pulses controlling the read out of said sixth means at said repetition rate.

Claim 10

A time division multiplex pulse code modulation intelligence communication system, each pulse code modulation code combination having n bit positions, where n is an integer greater than three, one bit position being employed for signalling and/or synchronizing and (n-1) bit positions being employed for intelligence communication purposes, and capable of enabling the communication with binary data bits by employing said (n-1) bit positions of selected ones of the time division multiplex channels comprising: a source of binary data bits in a time division multiplex format to be transmitted; first means coupled to said source to store said binary data bits; second means coupled to said source to count the number of said binary data bits stored during the time interval of a time division multiplex channel of said format, said number not exceeding (n-2); third means coupled to said first and second means to combine said stored binary data bits and a single marker bit, to substitute said stored binary data bits and said marker bit for said (n-1) bit positions of normal intelligence in one of said time division multiplex channels, and to group said stored binary data bits and said marker bit together at one end of said (n-1) bit positions with said marker bit being disposed in the bit position immediately following the last bit of said stored binary data bits so that the location of said marker bit within said (n-1) bit positions defines the number and repetition rate of said stored binary data bits associated therewith; fourth means coupled to said third means to transmit a combination of said one bit position, said stored binary data bits and said marker bit; fifth means coupled to said fourth means to receive said transmitted combination; sixth means coupled to said fifth means to store said marker bit and said binary data bits; and seventh means coupled to said fifth and sixth means to generate clock pulses having a repetition rate as determined by said location of said marker bit within said (n-1) bit positions, said clock pulses controlling the read out of said sixth means at said repetition rate.

Claim 11

A system according to claim 7, wherein said first means includes a shift register having (n-2) stages.

Claim 12

A system according to claim 7, wherein said second means includes eigth means coupled to said source to generate clock pulses in synchronism with said binary data bits, each of said clock pulses controlling the insertion of one of said binary data into said first means, ninth means coupled to said eigth means to count said clock pulses, and tenth means coupled to said first means and said ninth means to compare the number of said binary data bits stored in said first means with the count of said ninth means and to insert said marker bit in the proper location within said (n-1) bit positions and clear said first and ninth means when said number and said count agree.

Claim 13

A system according to claim 7, wherein a plurality of said time division multiplex channels contain said Transmitted combination, and said sixth means includes two shift registers each having (n-1) stages, said shift registers being employed alternately on alternate frames of the time division multiplex signal.