Data signal transmission system employing phase modulation

Claim 1

A phase modulation data transmission system, comprising a transmitter including: a source of a data input serial binary signal consisting of a predetermined number of bits occurring at a preselected repetitive frequency; a generator of a plurality of timing signals; means connected to said source and generator and responsive to first and second of said timing signals for converting said predetermined number of input serial bits into a corresponding number of parallel signals, each pair of said serial bits being converted into one pair of said parallel signals; first and second phase set circuits having inputs connected to first and second outputs, respectively, of said converting means for utilizing a first pair of said parallel signals under control of a third of said timing signals to provide predetermined different amounts of phase shift in first and second portions, respectively, of a carrier signal having a preassigned frequency to represent corresponding first and second bits in said input serial binary signal; third and fourth phase set circuits having inputs connected to third and fourth outputs, respectively, of said converting means for utilizing a second pair of said parallel signals under control of said third timing signal to provide further predetermined different amounts of phase shift in third and fourth portions, respectively, of said carrier signal to represent corresponding third and fourth bits in said input serial binary signal; first and second envelope modulators having inputs connected to outputs of said first and second phase set circuits, respectively, for shaping said phase shifted first and second carrier signal portions into approximately sine waves under control of a fourth of said timing signals; third and fourth envelope moduators having inputs connected to outputs of said third and fourth phase set circuits, respectively, for shaping said phase shifted third and fourth carrier signal portions into approximately sine waves under control of said fourth timing signal; first and second OR circuits, each having first and second inputs and an output; said first OR circuit first and second inputs connected to outputs of said first and second modulators, respectively; said second OR circuit first and second inputs connected to outputs of said third and fourth modulators, respectively; and combiner circuit means having inputs connected to said first and second OR circuit outputs and including an output terminal for combining at said output terminals said output terminals said first through fourth carrier signal portion sine waves as derived from said first and second OR circuit outputs to represent said first through fourth bits in said input serial binary signal; said combiner circuit means also combining at said output terminal a fifth timing signal identical with said fourth timing signal; and a receiver for receiving said combined first through fourth carrier signal portion sine waves and said fifth timing signal from said combiner means output terminal to derive from said last-mentioned waves and signal an output data serial binary signal having said input serial binary signal predetermined number of bits as a reproduction of said input data serial binary signal having said predetermined number of bits; said receiver comprising: amplifying means having an input connected to said combiner means output terminal for amplifying said sine waves and fifth timing signal received therefrom; timing signal extracting means having an input connected to an output of said amplifying means for deriving from said amplified fifth timing signal a direct current control signal which is produced in an output of said extracting means and applied to another input of said amplifying means to maintain said amplified waves and fifth timing signal at a certain level; first and second phase shifters having inputs connected to said amplifying means output for further shifting by first and second preselected different fixed amounts the phase of said amplified sine waves to provide further phase shifted sine waves; third and fourth phase shifters having inputs connected to said amplifying means output for further shifting by third and fourth preselected different fixed amounts the phase of said amplified sine waves to provide further phase shifted sine waves; delay circuit means having an input connected to said amplifying means output for providing a time delay equal to four of said input signal bits in said amplified sine waves to produce a reference phase signal; first and second phase detectors having inputs connected to outputs of said first and second phase shifters, respectively, and an output of said delay means for detecting the phase difference between said further phase shifted sine waves in said outputs of said first and second phase shifters, respectively, and said time delayed sine waves to produce first and second phase difference signals in outputs of said respective first and second phase detectors; third and fourth phase detectors having inputs connected to outputs of said third and fourth phase shifters, respectively, and said output of said delay means for detecting the phase difference between said further phase shifted sine waves in said outputs of said third and fourth phase shifters, respectively, and said time delayed sine waves to produce third and fourth phase difference signals in outputs of said respective third and fourth phase detectors; amplitude comparing means having inputs connected to said amplifying means output and said timing extracting means output for comparing a direct current amplitude representing other phase detection of said amplified sine waves derived from said amplifying means output and the amplitude of said direct current control signal derived from said timing extracting means output to produce amplitude difference signals in an output of said amplitude comparing means; a second generator of timing signals having an input coupled to another output of said timing extracting means for producing in an output of said second generator a plurality of further timing signals having frequencies different from and higher than the frequency of said fifth timing signal derived from said timing extracting means another output; and sampling means having inputs connected to said comparing means output and said second generator output and additional sampling means having inputs coupled to said first through fourth phase detector outputs and said seCond generator output for control by said further timing signals to translate said amplitude difference signals and said phase difference signals into said output data serial binary signal as said reproduction input data serial binary signal.