Fet dynamic logic circuit and layout

Claim 2

A set of field effect transistor circuits formed upon a single semiconductor substrate of a first conductivity type comprising a plurality of diffusions of a semiconductor material of opposite conductivity type upon said substrate in substantially parallel relationship including a plurality of interconnected stages of FET devices with a plurality of FET devices per stage, a plurality of dynamic logic clock phase lines extending in transverse relationship with respect to said diffusions and connected to said diffusions and forming FET gates with said diffusions, and a plurality of coupling lines, said clock phase lines and coupling lines forming gates or contacts with said diffusions being superposed upon said diffusions said clock phase lines being connected to a source of clock signals recurring in a regular predetermined sequence.

Claim 3

Apparatus in accordance with claim 1 including a plurality of stages of transistor circuits, with only one clock phase line connected to the gate and one other electrode of an FET device in each stage, wherein a stage includes at least two FET devices formed by a pair of parallel diffusions with at least one gate formed by said clock phase line between said diffusions and a coupling line for connection to a source of data, said coupling line also forming the gate of another FET of said stage.

Claim 4

A set of circuits in accordance with claim 1 wherein said clock phase lines cross said diffusions intermediate opposite ends thereof.

Claim 5

A multi-stage FET circuit configuration including a plurality of stages having a plurality of clock phase input lines, with a pair of FET devices in each stage, with the drain and gate of one FET and the source of the other FET connected to the clock phase input line of the stage, and the remaining source of the one FET and drain of the other FET connected together and having a data output therefrom, with a data input to the gate of the other FET, each of said clock phase input lines being adapted to be connected to a plurality of clock phase signals supplied in a cyclical fashion with n clock phase intervals pEr cycle where n > or = 5, with only one clock phasesignal occurring for each said interval with a first plural FET stage of the circuit having a plurality of FET devices, connected to a first clock phase signal with the output of said first stage connected to the input of a second plural FET stage having a plurality of FET devices connected to a clock phase signal occurring Alpha clock phase intervals later than said first clock phase signal, where Alpha is an integer greater than zero and less than b clock pulse intervals, and b is an integer greater than Alpha and less than or equal to four, with some successive stages connected to nonconsecutive clock phase signals.

Claim 6

A multi-stage FET circuit configuration including a plurality of stages having a plurality of clock phase input lines, with a pair of FET devices in each stage, with the drain and gate of one FET and the source of the other FET connected to the clock phase input line of the stage, and the remaining source of the one FET and drain of the other FET connected together and having a data output therefrom, with a data input to the gate of the other FET, each of said clock phase input lines being adapted to be connected to a plurality of clock phase signals supplied in a cyclical fashion with n clock phase intervals pEr cycle where n > or = 5, with only one clock phasesignal occurring for each said interval with a first plural FET stage of the circuit having a plurality of FET devices, connected to a first clock phase signal with the output of said first stage connected to the input of a second plural FET stage having a plurality of FET devices connected to a clock phase signal occurring Alpha clock phase intervals later than said first clock phase signal, where Alpha is an integer greater than zero and less than b clock pulse intervals, and b is an integer greater than Alpha and less than or equal to four, with some successive stages connected to nonconsecutive clock phase signals.

Claim 7

Apparatus comprising a plurality of FET, semiconductor circuits formed on a single substrate, said circuits including a plurality of interconnected stages of FET devices wherein each stage includes a pair of FET devices, with the drain and gate of one FET and the source of the other FET connected to the clock phase input line of the stage and the remaining source of the one FET and drain of the other FET connected together and having a data output therefrom, with a first data input to the gate of the other FET, said circuits including a plurality of clock lines and a plurality clock line terminals, time being divided into n clock phase intervals per cycle, where n is an integer greater than 4, only one clock line being connected to control each of said stages of said circuits with the output of each said stage being connected to another one of said stages controlled by different one of said clock lines with the clock lines having a cyclical sequence of clock phase signals thereon with the output of a first stage connected to the input of a second stage having a clock phase signal which occurs Alpha clock phase intervals later than the clock phase signal of the first stage where Alpha is an integer greater than zero and less than b, where b is an integer less than or equal to n-2 and greater than zero, and the output of the second stage is connected to the input of a third stage having a clock phase signal which occurs b clock phase intervals later than the clock phase signal of the first stage, with at least some successive staes connected to nonconsecutive clock phase signals.

Claim 8

Apparatus comprising a plurality of FET, semiconductor circuits formed on a single substrate, said circuits including a plurality of interconnected stages of FET devices wherein each stage includes a pair of FET devices, with the drain and gate of one FET and the source of the other FET connected to the clock phase input line of the stage and the remaining source of the one FET and drain of the other FET connected together and having a data output therefrom, with a first data input to the gate of the other FET, said circuits including a plurality of clock lines and a plurality clock line terminals, time being divided into n clock phase intervals per cycle, where n is an integer greater than 4, only one clock line being connected to control each of said stages of said circuits with the output of each said stage being connected to another one of said stages controlled by different one of said clock lines with the clock lines having a cyclical sequence of clock phase signals thereon with the output of a first stage connected to the input of a second stage having a clock phase signal which occurs Alpha clock phase intervals later than the clock phase signal of the first stage where Alpha is an integer greater than zero and less than b, where b is an integer less than or equal to n-2 and greater than zero, and the output of the second stage is connected to the input of a third stage having a clock phase signal which occurs b clock phase intervals later than the clock phase signal of the first stage, with at least some successive staes connected to nonconsecutive clock phase signals.

Claim 9

A set of FET circuits combined into a system including separate stages of FET circuits and a plurality of clock phase lines wherein at least two FET devices are included in each stage and a single one of said clock phase lines is connected to each stage, wherein at least two interconnected stages are connected to clock phase lines which are nonconsecutive, each stage including an FET device having its gate and one other electrode connected to one of said clock phase lines and having its third electrode connected at a junction to an electrode other than the gate of a second FET device with said gate of said second FET device adapted to be connected to a source of data.

Claim 10

A set of FET circuits combined into a system including separate stages of FET circuits and a plurality of clock phase lines wherein at least two FET devices are included in each stage and a single one of said clock phase lines is connected to each stage, wherein at least two interconnected stages are connected to clock phase lines which are nonconsecutive, each stage including an FET device having its gate and one other electrode connected to one of said clock phase lines and having its third electrode connected at a junction to an electrode other than the gate of a second FET device with said gate of said second FET device adapted to be connected to a source of data.

Claim 11

Apparatus in accordance with claim 6 wherein said junction is adapted to be connected to the gate of another stage.

Claim 12

Apparatus in accordance with claim 6 wherein an FET device having one of its electrodes other than its gate connected to said clock phase line and the remaining one of its electrodes connected in a series circuit with said third electrode of said first FET.