Coder-decoder for use in a delta-transmission system

Claim 2

A transmitter for use in a delta modulation system, comprising clock pulse generator means, a pulse code modulator controlled by the generator and comprising a bistable trigger circuit of the type capable of changing its conduction state under the control of an input signal at any time during the duration of a clock pulse applied thereto, signal comparison means, means for coupling an analog signal as a first input to said comparison means, means coupling said comparison means to said pulse code modulator, means for deriving a first output signal from said modulator, means for integrating said first signal and for applying the same to said comparison means, means for deriving a second output signal from said modulator, means for differentiating said second output signal from said modulator and means for applying said differentiated second output signal to said comparison means as a positive feedback voltage pulse whereby the dIfferentiated second output signal is superimposed on the difference signal supplied by said comparison means to said modulator.

Claim 3

A transmitter as claimed in claim 1, wherein said means for applying said second output signal comprises a resistor and a capacitor in series connection.

Claim 4

A transmitter as claimed in claim 1, wherein said means for applying said second output signal comprises a feedback loop, and wherein the differentiating means comprises means for providing a feedback pulse having a duration exceeding the clock pulse duration.

Claim 5

A transmitter as claimed in claim 1, wherein the ratio of the duration of the clock pulse to the period between clock pulses is less than 0.5.

Claim 6

A transmitter as claimed in claim 1, wherein the bistable circuit comprises an input transistor, said input transistor operating as a switch under the control of the clock pulse and directing the difference signal to ground during the absence of a clock pulse and directing the difference signal to two cascade connected transistors during the clock pulse, said cascade connected transistors producing complementary output pulses, means comprising a diode and a resistor coupled to said two cascade connected transistors for permitting the cascade transistors to operate as an amplifier for the difference signal in response to the presence of a clock pulse and for maintaining the transistors in the state occupied at the end of the period of the first of the two clock pulses in response to the absence of a clock pulse.

Claim 7

A transmitter as claimed in claim 1, wherein the means for deriving a first output signal from said modulator comprises an amplitude modulator, said amplitude modulator comprising two complementary transistors operating each as a current generator for charging and discharging the integrator.

Claim 8

A transmitter as claimed in claim 6, further comprising a compression circuit for controlling the amplitude modulator, said compression circuit comprising two input means each of which includes a diode and a resistance-acapacitance circuit, means to couple an output signal of the pulse code modulator as one input signal to the compression circuit, means to couple a complementary output signal of said pulse code modulator as a second input signal to the compression circuit, said compression circuit comprising a comparison circuit for supplying compression controlled pulses when the voltage at one of the capacitors in the two RC circuits exceeds a given threshold.

Claim 9

A receiver for use in a delta modulation transmission system comprising a clock pulse generator; a bistable trigger controlled by the generator; an expansion circuit coupled to the output of the bistable trigger; an amplitude modulator having an output current corresponding to an input signal; means to couple an output of the expansion circuit as an input signal to the amplitude modulator; and an integrator coupled to the output of the amplitude modulator; said bistable circuit comprising an input transistor and two cross coupled transistors connected to the input transistor, said input transistor operating as a switch under the control of the clock pulses and directing the received signals to ground potential during the absence of clock pulses and directing the received signals to the two cascade connected transistors during the interval of the clock pulse, and a network of diodes and resistors comprising the cross coupling of the cross coupled transistors so that the two transistors operate as an amplifier during a clock pulse and so that during the time between two consecutive clock pulses the two transistors remain in the state occupied at the end of the first of the two clock pulses.

Claim 10

A receiver for use in a delta modulation transmission system comprising a clock pulse generator; a bistable trigger controlled by the generator; an expansion circuit coupled to the output of the bistable trigger; an amplitude modulator having an output current corresponding to an input signal; means to couple an output of the expansion circuit as an input signal to the amplitude modulator; and an integrator coupled to the output of the amplitude modulator; said bistable circuit comprising an input transistor and two cross coupled transistors connected to the input transistor, said input transistor operating as a switch under the control of the clock pulses and directing the received signals to ground potential during the absence of clock pulses and directing the received signals to the two cascade connected transistors during the interval of the clock pulse, and a network of diodes and resistors comprising the cross coupling of the cross coupled transistors so that the two transistors operate as an amplifier during a clock pulse and so that during the time between two consecutive clock pulses the two transistors remain in the state occupied at the end of the first of the two clock pulses.

Claim 11

A receiver as claimed in claim 8, wherein the amplitude modulator comprises complementary transistors operating each as a current generator for charging and discharging the integrator.

Claim 12

A receiver as claimed in claim 8, wherein the expansion circuit comprises two input circuits, each input circuit of the expansion circuit comprising a diode coupled to a RC circuit, the expansion circuit being coupled to the bistable circuit so that the bistable circuit provides a separate input signal to each of the input circuits of the expansion circuit, said expansion circuit further comprising a comparison circuit for supplying controlled pulses for the amplitude modulator when the voltage at one of the capacitors exceeds a given threshold.