Abstract A circuit for protecting an insulated gate field-effect transistor (IGFET) circuit from damage caused by spurious, high voltage inputs resulting primarily from static charge is made up of a pair of IGFET''s. A first protection circuit IGFET has a drain connected to the gate of at least one main circuit IGFET to be protected, the gate of the main circuit IGFET being connected to an input terminal. The source of the first protection circuit IGFET is connected to a common reference. The gate of the first protection circuit IGFET is connected to the drain of a second protection circuit IGFET whose source is connected to the common reference and whose gate is connected to a discharge terminal for applying a voltage to the gate sufficient to turn on the second protection circuit IGFET. The first protection circuit IGFET goes into an avalanche condition when a spurious signal of a polarity to cause a reverse bias is of sufficient amplitude to start an injection of carriers from the drain to the gate. The avalanche condition is maintained until the drain voltage drops below the avalanche maintenance value. The charge on the gate of the first protection circuit IGFET may or may not leak off by the time the circuit is ready for testing. Whether the charge has leaked off or not is of no consequence because when the circuit is connected to the tester, a voltage is applied to the gate of the second protection circuit IGFET turning it on and causing the charge on the gate, if any, of the first protection circuit IGFET to be conducted to ground.
An integrated, input protection circuit, formed upon a substrate, having input means connected to the gate of at least one main circuit insulated gate field-effect transistor to be protected from spurious, high amplitude voltage signals, comprising: a. a protection circuit insulated gate field-effect transistor having a gate, and having a drain connected to the input means and the source connected to a common terminal for injection of carriers from the drain to the gate in an avalanche mode to charge the gate when a spurious signal of a reverse bias polarity is received; b. a second protection circuit insulated gate field-effect transistor whose drain is connected to the gate of the first protection circuit insulated gate field-effect transistor, its source is connected to the common terminal and its gate is connected to the discharge terminal, and having a control electrode for selectively causing the second protection circuit insulated gate field-effect transistor to conduct; and c. a discharge terminal connected to the gate of the second protection circuit insulated gate field-effect transistor for applying a potential to the control electrode to cause the second protection circuit insulated gate field-effect transistor to conduct.
Claim 2
Dependent Claim
191 words
An integrated, input protection circuit, formed upon a substrate, having input means connected to the gate of at least one main circuit insulated gate field-effect transistor to be protected from spurious, high amplitude voltage signals, comprising: a. a protection circuit insulated gate field-effect transistor having a gate, and having a drain connected to the input means and the source connected to a common terminal for injection of carriers from the drain to the gate in an avalanche mode to charge the gate when a spurious signal of a reverse bias polarity is received; b. a second protection circuit insulated gate field-effect transistor whose drain is connected to the gate of the first protection circuit insulated gate field-effect transistor, its source is connected to the common terminal and its gate is connected to the discharge terminal, and having a control electrode for selectively causing the second protection circuit insulated gate field-effect transistor to conduct; and c. a discharge terminal connected to the gate of the second protection circuit insulated gate field-effect transistor for applying a potential to the control electrode to cause the second protection circuit insulated gate field-effect transistor to conduct.
Claim 3
Dependent Claim
30 words
The circuit of claim 1 wherein the second protection circuit insulated gate field-effect transistor has a channel conductivity type complementary to that of the protection circuit insulated gate field-effect transistor.
Claim 4
Dependent Claim
23 words
The circuit of claim 1 wherein the channel conductivity of the first and second protection circuit insulated gate field-effect transistors is the same.
Claim 5
Dependent Claim
26 words
The circuit of claim 3 wherein the main circuit and the first and second protection circuit insulated gate field-effect transistors are of the P-channel conductivity type.
Claim 6
Dependent Claim
23 words
The circuit of claim 3 wherein the main circuit and first and second protection circuit insulated gate field-effect transistors are of MOS type.
Claim 7
Dependent Claim
18 words
The circuit of claim 2 wherein the main circuit and the protection circuit are comprised of CMOS devices.