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US3745539A Expired / Lapsed US ⏱️ 0.0 years remaining

Latch type regenerative circuit for reading a dynamic memory cell

Assignee: International Business Machines Corp
•
Filing: 1972-03-20
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Granted: 1973-07-10
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Expires: 1992-03-20
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Abstract

Abstract A semiconductor device circuit for reading an FET capacitor store dynamic memory cell and for regenerating the charge (if any) in said capacitor whereby non-destructive read-out is achieved. The memory cell includes an FET switch for selectively connecting the storage capacitor to a memory array bit-sense line through either one of a pair of oppositely connected bipolar transistors for reading and writing, respectively. The bit-sense line is connected to the input terminal of a latching regenerative feedback amplifier such as a silicon controlled rectifier. The potential level at said input terminal rises to a relatively higher level by regenerative feedback action in response to a relatively lower bit-sensing voltage which initiates the latching action. The storage capacitor of the memory cell is recharged via one of the bipolar transistors in response to the aforesaid relatively higher potential at the the amplifier input terminal. Bipolar current switch embodiments as well as a silicon controlled rectifier embodiment are disclosed for instrumenting the latching regenerative feedback amplifier.

Inventors

  • 👤 E Davidson
  • 👤 R Lane
  • 👤 J Saia

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 12:18
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; H; H03; H03K; H03K5/00; H03K5/01; H03K5/02

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 132 words
In combination, a latching circuit for reading a capacitor store memory cell and for regenerating any charge lost from said cell, said cell being connected to a common read-write line through a pair of unidirectionally conductive devices poled to conduct current in opposite directions with respect to said capacitor and connected in parallel with respect to each other, at least one of said devices producing current gain, said cell comprising a capacitor and an actuatable switch for selectively connecting said capacitor to said line through said pair of devices, said latching circuit having an input terminal connected to said line and possessing the characteristic that upon latching, the voltage level at said input terminal is driven by positive feedback action to a value above the threshold at which latching action is initiated.
Claim 2
Dependent Claim 132 words
In combination, a latching circuit for reading a capacitor store memory cell and for regenerating any charge lost from said cell, said cell being connected to a common read-write line through a pair of unidirectionally conductive devices poled to conduct current in opposite directions with respect to said capacitor and connected in parallel with respect to each other, at least one of said devices producing current gain, said cell comprising a capacitor and an actuatable switch for selectively connecting said capacitor to said line through said pair of devices, said latching circuit having an input terminal connected to said line and possessing the characteristic that upon latching, the voltage level at said input terminal is driven by positive feedback action to a value above the threshold at which latching action is initiated.
Claim 3
Dependent Claim 30 words
The combination defined in claim 1 wherein said one of said devices is a bipolar transistor having an emitter connected to said line and a base connected to said switch.
Claim 4
Dependent Claim 74 words
The combination defined in claim 1 wherein both of said devices are bipolar transistors each having an emitter, a base and a collector and further including a voltage source, the emitter of one and the base of the other transistor being connected to said switch, the emitter of said other and the base of said one transistor being connected to said line, and the collectors of said transistors being connected to said voltage source.
Claim 5
Dependent Claim 15 words
The combination defined in claim 1 wherein said latching circuit comprises a silicon controlled rectifier.
Claim 6
Dependent Claim 29 words
The combination defined in claim 1 wherein said switch is a field effect transistor, both said devices are bipolar transistors and said latching circuit is a silicon controlled rectifier.
Claim 7
Dependent Claim 39 words
The combination defined in claim 1 including a plurality of said capacitor store memory cells wherein a plurality of said capacitor store memory cells are connected to said common read-write line through the same pair of unidirectional conductive devices.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-07-09 1977-01-08 1977-07-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-07-09 1981-01-08 1981-07-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-07-09 1985-01-08 1985-07-10 $7700.00 Window Closed / Lapsed

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