Patent US3745472A successfully refreshed from Google Patents.
US3745472A
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Synchronous digital system having a clock distribution system
Assignee: Texas Instruments Inc
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Filing: 1971-07-01
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Granted: 1973-07-10
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Expires: 1991-07-01
Abstract
Abstract A clock distribution system within a synchronous digital system, such as a digital data processing system, permits adjustment of clock pulse width and time occurrence at each individual logic card within the system. An oscillator generates a clock signal having a pulse width larger than the desired clock pulse width. This generated clock signal is distributed through a plurality of fanout circuits to a plurality of logic cards located throughout the system. On each logic card a first adjustable delay line permits time delay adjustment to realign waveform transitions and thus synchronize the system. This time-aligned signal is then connected to one input of an AND gate and also is inverted and connected through a second adjustable delay line to the other input of the AND gate, thus permitting selective control of the clock pulse width.
Inventors
- 👤 E Garth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017545; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
285 words
A synchronous digital system compriSing: a. means for generating a clock signal; b. a plurality of locations within said system; c. means for distributing said clock signal to said plurality of locations; d. at each of said locations, first time delay means coupled to said clock signal for introducing a first predetermined time delay thereto, thereby synchronizing the occurrence of said clock signal at each of said locations; e. first logic means coupled to the output of said first time delay means, said first logic means having an inverted output and a non-inverted output; f. second time delay means connected to at least one of said inverted output and said noninverted output for introducing a second predetermined time delay thereto, said second time delay means is connected only to said inverted output; and g. second logic means coupled for combining said inverted output and said noninverted output to produce a plurality of multiphased clock signals, each pulse of each phase having a controlled width, said second logic means comprises: 1. a third logic means connected to said noninverted output of said first logic means, said third logic means having an inverted output and a noninverted output; 2. fourth logic means connected to the output of said second time delay means, said fourth logic means having an inverted output and a noninverted output; 3. a plurality of fifth logic means coupled to combine the inverted outputs of said third and fourth logic means to produce a first phase clock signal of controlled pulse width; and 4. a plurality of sixth logic means coupled to combine the noninverted outputs of said third and fourth logic means to produce a second phase clock signal of controlled pulse width.
Claim 2
Dependent Claim
285 words
A synchronous digital system compriSing: a. means for generating a clock signal; b. a plurality of locations within said system; c. means for distributing said clock signal to said plurality of locations; d. at each of said locations, first time delay means coupled to said clock signal for introducing a first predetermined time delay thereto, thereby synchronizing the occurrence of said clock signal at each of said locations; e. first logic means coupled to the output of said first time delay means, said first logic means having an inverted output and a non-inverted output; f. second time delay means connected to at least one of said inverted output and said noninverted output for introducing a second predetermined time delay thereto, said second time delay means is connected only to said inverted output; and g. second logic means coupled for combining said inverted output and said noninverted output to produce a plurality of multiphased clock signals, each pulse of each phase having a controlled width, said second logic means comprises: 1. a third logic means connected to said noninverted output of said first logic means, said third logic means having an inverted output and a noninverted output; 2. fourth logic means connected to the output of said second time delay means, said fourth logic means having an inverted output and a noninverted output; 3. a plurality of fifth logic means coupled to combine the inverted outputs of said third and fourth logic means to produce a first phase clock signal of controlled pulse width; and 4. a plurality of sixth logic means coupled to combine the noninverted outputs of said third and fourth logic means to produce a second phase clock signal of controlled pulse width.
Claim 3
Dependent Claim
15 words
The system of claim 1 wherein said fifth and sixth logic means are AND gates.
Claim 4
Dependent Claim
25 words
fourth logic means connected to the output of said second time delay means, said fourth logic means having an inverted output and a noninverted output;
Claim 5
Dependent Claim
25 words
fourth logic means connected to the output of said second time delay means, said fourth logic means having an inverted output and a noninverted output;
Claim 6
Dependent Claim
31 words
a plurality of fifth logic means coupled to combine the inverted outputs of said third and fourth logic means to produce a first phase clock signal of controlled pulse width; and
Claim 7
Dependent Claim
31 words
a plurality of fifth logic means coupled to combine the inverted outputs of said third and fourth logic means to produce a first phase clock signal of controlled pulse width; and
Claim 8
Dependent Claim
30 words
a plurality of sixth logic means coupled to combine the noninverted outputs of said third and fourth logic means to produce a second phase clock signal of controlled pulse width.
Claim 9
Dependent Claim
30 words
a plurality of sixth logic means coupled to combine the noninverted outputs of said third and fourth logic means to produce a second phase clock signal of controlled pulse width.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-09 | 1977-01-08 | 1977-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-09 | 1981-01-08 | 1981-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-09 | 1985-01-08 | 1985-07-10 | $7700.00 | Window Closed / Lapsed |